JPS63127129U - - Google Patents

Info

Publication number
JPS63127129U
JPS63127129U JP1987018937U JP1893787U JPS63127129U JP S63127129 U JPS63127129 U JP S63127129U JP 1987018937 U JP1987018937 U JP 1987018937U JP 1893787 U JP1893787 U JP 1893787U JP S63127129 U JPS63127129 U JP S63127129U
Authority
JP
Japan
Prior art keywords
silicon chip
sealed
resin
integrated circuit
lead frame
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1987018937U
Other languages
English (en)
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1987018937U priority Critical patent/JPS63127129U/ja
Publication of JPS63127129U publication Critical patent/JPS63127129U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612Auxiliary members for layer connectors, e.g. spacers

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Die Bonding (AREA)
JP1987018937U 1987-02-10 1987-02-10 Pending JPS63127129U (US06826419-20041130-M00005.png)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987018937U JPS63127129U (US06826419-20041130-M00005.png) 1987-02-10 1987-02-10

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987018937U JPS63127129U (US06826419-20041130-M00005.png) 1987-02-10 1987-02-10

Publications (1)

Publication Number Publication Date
JPS63127129U true JPS63127129U (US06826419-20041130-M00005.png) 1988-08-19

Family

ID=30813073

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987018937U Pending JPS63127129U (US06826419-20041130-M00005.png) 1987-02-10 1987-02-10

Country Status (1)

Country Link
JP (1) JPS63127129U (US06826419-20041130-M00005.png)

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