JPS6312156A - Minute pattern forming method - Google Patents

Minute pattern forming method

Info

Publication number
JPS6312156A
JPS6312156A JP15654586A JP15654586A JPS6312156A JP S6312156 A JPS6312156 A JP S6312156A JP 15654586 A JP15654586 A JP 15654586A JP 15654586 A JP15654586 A JP 15654586A JP S6312156 A JPS6312156 A JP S6312156A
Authority
JP
Japan
Prior art keywords
resist
photoresist
electrode
dimensional
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15654586A
Other languages
Japanese (ja)
Inventor
Katsuya Ozaki
小崎 克也
Yoshinobu Sasaki
善伸 佐々木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP15654586A priority Critical patent/JPS6312156A/en
Publication of JPS6312156A publication Critical patent/JPS6312156A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To form a three-dimensional minute pattern of a desired configuration in a simple and reproducible manner by depositing metal using a mask composed of a three-dimensional resist profile obtained by two exposure processes under different conditions. CONSTITUTION:Positive type photoresist 6 is thickly applied on a GaAs substrate 1, on which an electrode 2 is formed. A converging ion beam is selectively projected, and a desired range of the resist 6 is exposed to a desired thickness. Then an ion beam accelerated by a voltage higher than that in the previous process is projected to the resist 6 in the range where the electrode 2 is formed. The resist 6 is exposed to the interface with the electrode 2. Then, development is performed, and a three-dimensional resist profile is obtained. Thereafter, metal is evaporated, and a metal deposited layer 7 is formed. Lift-off is performed, and a three-dimensional minute pattern is obtained. Thus, reproducibility is improved.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、半導体基板上への微細パターン形成方法に
関し、特にGaAs基板上へのエアブリッジの形成方法
に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for forming fine patterns on a semiconductor substrate, and particularly to a method for forming an air bridge on a GaAs substrate.

〔従来の技術〕[Conventional technology]

第2図(a)〜(J)は従来の半導体基板上への橋状の
立体的金属微細パターン(エアブリッジ)形成方法の主
要製造工程を示す断面図で、以下これを用いて従来の方
法を説明する。第2図において、1は半導体基板、2は
電極、3および33はネガ型フォトレジスト 44は第2スパッタ金属層、5は第1メッキ金属層、5
5は第2メッキ金属層、6および66はポジ型フォトレ
ジストである。
Figures 2 (a) to (J) are cross-sectional views showing the main manufacturing steps of a conventional method for forming a bridge-like three-dimensional metal fine pattern (air bridge) on a semiconductor substrate. Explain. In FIG. 2, 1 is a semiconductor substrate, 2 is an electrode, 3 and 33 are negative photoresists 44 are second sputtered metal layers, 5 is a first plated metal layer, 5
5 is a second plated metal layer, and 6 and 66 are positive photoresists.

次に製造工程について説明する。Next, the manufacturing process will be explained.

まず、第2図(a)に示すように、半導体基板1上に所
要数の電極2を形成後、ネガ型フォトレジスI− 3を
塗布し、写真製版によって前記ネガ型フォトレジスト ツクリングデポジションを行って第1スパッタ金属層4
を形成する。ここで、スバソタリングデボジンヨンとは
、スパッタリングによって削られたターゲット金属を堆
積させる金属形成法である。
First, as shown in FIG. 2(a), after forming a required number of electrodes 2 on a semiconductor substrate 1, a negative type photoresist I-3 is applied, and the negative type photoresist is then deposited by photolithography. to form the first sputtered metal layer 4
form. Here, the subsotering deposition is a metal forming method in which target metal scraped by sputtering is deposited.

次に、第2図(b)に示すように、ネガ型フォトレジス
ト ガ型フォトレジスト33をバターニングする。次に、第
2図(C)に示すように、電解メッキを行って第1メッ
キ金属層5を形成し、その後、第2図(d)に示すよう
に、ネガ型フォトレジスト3および33を除去してエア
ブリッジの橋げた部分を形成する。続いて、第2図(e
)に示すように、ポジ型フォトレジスト6 示すように、写真製版によって前記ポジ型フォトレジス
ト6 g)に示すように、スパッタリングデポジションを行い
、第2スパッタ金属層44を形成する。第2図(g)の
状態の後、第2図(h)に示すように,第2スパッタ金
属層44の上に、さらにポジ型フォ)・レジス)・66
を塗布し、写真製版によってバターニングする。その後
、第2図(i)に示すように、電解メッキを行って第2
メッキ金属層55を形成し、最後にポジ型フォI・レジ
スト6および66を除去して、第2図(])に示すよう
なエアブリッジを形成する。ここで、第1スパッタ金属
層4および第2スパッタ金属層44は、それぞれ第1メ
ッキ金属層5および第2メッキ金属層55を形成する工
程において、半導体基板1をカソード電極となして電解
メッキを行うための下地金属層として機能している。
Next, as shown in FIG. 2(b), the negative type photoresist 33 is patterned. Next, as shown in FIG. 2(C), electrolytic plating is performed to form a first plated metal layer 5, and then, as shown in FIG. 2(d), negative photoresists 3 and 33 are applied. Remove it to form the girder part of the air bridge. Next, Figure 2 (e
) As shown in g), the positive photoresist 6 is formed by photolithography. Sputtering deposition is performed as shown in g) to form a second sputtered metal layer 44. After the state shown in FIG. 2(g), as shown in FIG. 2(h), a positive photoresist 66 is further applied on the second sputtered metal layer 44.
is coated and buttered by photolithography. After that, as shown in Fig. 2(i), electrolytic plating is performed to form a second plate.
A plated metal layer 55 is formed, and finally the positive photo resists 6 and 66 are removed to form an air bridge as shown in FIG. 2 ( ). Here, the first sputtered metal layer 4 and the second sputtered metal layer 44 are formed by electroplating using the semiconductor substrate 1 as a cathode electrode in the step of forming the first plated metal layer 5 and the second plated metal layer 55, respectively. It functions as a base metal layer for the process.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

従来の半導体基板1上への金属微細パターン形成方法に
よると、第2図(a)ないし第2図(j)のように非常
に工程数が多く複雑で、特に写真製版を4回行わなくて
はならないため(第2図(a)の第1スパッタ金属層4
を形成する前の工程,および第2図(b )、 (F 
L (h )の工程における計4回)、マスク合わせを
繰り返すごとにアライメント精度が低下していき、マス
クずれが生じ易く、エアブリッジの外観不良を引き起こ
すという問題点かあった。
According to the conventional method of forming fine metal patterns on the semiconductor substrate 1, the number of steps is extremely large and complicated as shown in FIGS. (first sputtered metal layer 4 in FIG. 2(a)
2(b), (F
There was a problem in that each time the mask alignment was repeated (four times in total in the step L (h)), the alignment accuracy decreased, mask displacement was likely to occur, and the appearance of the air bridge was poor.

この発明は、上記のような問題点を解消するためになさ
れたもので、従来の複雑な工程を簡単化し、かつ形状の
慢れたエアブリッジを再現性よく形成することを目的と
する。
The present invention was made to solve the above-mentioned problems, and aims to simplify the conventional complicated process and form an air bridge with a slender shape with good reproducibility.

〔問題点を解決するための手段〕[Means for solving problems]

この発明に係る微細パターン形成方法は、所要数の電極
が形成された半導体基板上にフォトレジスト 所望の範囲を1回目の露光工程で所定の深さに露光し、
その後、2回目の露光工程で電極の形成されている範囲
のフォトレジストを電極界面まで露光し、この二段階の
露光部分を現像後除去して立体的レジストプロファイル
を形成し、この立体的レレストプロファイルをマスクと
して金属蒸着を行い、蒸着金属層を形成し、リフトオフ
により残ったフォトレジスト 除去して、エアブリッジを形成するようにしたものであ
る。
The fine pattern forming method according to the present invention includes exposing a desired range of photoresist to a predetermined depth in a first exposure step on a semiconductor substrate on which a predetermined number of electrodes are formed;
After that, in the second exposure step, the photoresist in the area where the electrode is formed is exposed to light up to the electrode interface, and this two-step exposed area is removed after development to form a three-dimensional resist profile. Metal evaporation is performed using the profile as a mask to form a evaporated metal layer, and the remaining photoresist is removed by lift-off to form an air bridge.

〔作用〕[Effect]

この発明においては、フォトレジスト 異なる2回の露光工程によって感光させて立体的レジス
トプロファイルを形成するので、工程数が簡略化される
とともに、アライメント精度が向上し、高精度のエアブ
リッジが形成される。
In this invention, a three-dimensional resist profile is formed by exposing the photoresist to two different exposure processes, which simplifies the number of steps, improves alignment accuracy, and forms a highly accurate air bridge. .

〔実施例〕〔Example〕

第1図(a)〜(f)はこの発明の微細パターン形成方
法における主要製造工程を示す断面図で、この図で、1
は半導体基板、例えばGaAs基板、2は電極、6はポ
ジ型フォ)・レジスI−、6aはボッ型フォトレジスト
感光部分、7は蒸着金属層を示し、また第1図(b)お
よび(Q)中の矢印は、集束性イオンビーム(以下FI
Bという)の入射方向をそれぞれ表している。
FIGS. 1(a) to 1(f) are cross-sectional views showing the main manufacturing steps in the fine pattern forming method of the present invention.
1(b) and (Q) indicate a semiconductor substrate, for example a GaAs substrate, 2 an electrode, 6 a positive photoresist I-, 6a a bottom photoresist photosensitive portion, and 7 a vapor deposited metal layer. ) indicates a focused ion beam (FI
B) respectively represent the incident direction.

まず、第1図(a)に示すように、電極2を形成した後
のGaAs基板1にポジ型フォトレジスト6を比較的厚
めに(層厚的1μIT1)塗布した後、第1図(b)に
示すように、GaAs基板1上に塗布されたポジ型フォ
トレジスト6 イオン種B e”、ドーズ量1 、 O X 1 03
cm−2,加圧電圧100KeVなるFIBを選択的に
照射し、ポジ型フォトレジスト6を表面から約0.8μ
mの深さまで感光させる。次に、第1図(C)に示すよ
うに、電極2の形成されている範囲のポジ型フ、Tトレ
レスト6に、前工程よりも高い加速電圧(200KeV
)で、イオン種B a”、ドーズ量1.OX 103a
m−2なるFIBを選択的に照射し、前記ポジ型フォト
レジスト6を電極2との界面に至るまで完全に感光させ
た後、第1図(d)に示すように、現像を行って橋型の
い伏となるような立体的レジメ1−プロファイルを得る
。続いて、第1図(e)に示すように、金属蒸着を行い
、蒸着金属層7を形成し、その後、リフトオフ(ポジ型
フォトレジスト6 ようなエアブリッジを形成する。
First, as shown in FIG. 1(a), a positive photoresist 6 is applied relatively thickly (layer thickness: 1 μIT1) onto the GaAs substrate 1 on which the electrode 2 has been formed, and then as shown in FIG. 1(b). As shown in FIG. 1, a positive photoresist 6 coated on a GaAs substrate 1 has an ion species B e”, a dose of 1, and an O X 103.
By selectively irradiating the FIB with a pressure of 100 KeV at a pressure of 100 KeV, the positive photoresist 6 is deposited approximately 0.8μ from the surface.
Expose to a depth of m. Next, as shown in FIG. 1(C), a higher accelerating voltage (200 KeV
), ion species B a”, dose amount 1.OX 103a
After selectively irradiating the positive photoresist 6 with FIB 2 m-2 and completely exposing it to the interface with the electrode 2, development is performed to remove the bridges, as shown in FIG. 1(d). Three-dimensional regimen 1 - Obtain a profile that will become the shape of the kata. Subsequently, as shown in FIG. 1(e), metal evaporation is performed to form a evaporated metal layer 7, and then a lift-off (air bridge such as a positive photoresist 6) is formed.

上記実施例のように、ポジ型フォ)・レジスト6を感光
させる手段としてFEBを用いると、注入するイオン種
あるいは加速電圧等の条件を適当に選び、ポジ型フォト
レレストを所望の深さまで感光させろことによって、立
体的レジストプロファイルの形成が可能となる。この作
用を利用してこの実施例による方法では、第1図(b)
の工程で、まず、エアブリッジの橋状のい型となるべき
部分のポジ型フォトレジス1−6を感光させ、次いで第
1図(C)の工程で、エアブリッジの橋げたのい型とな
るべき部分のポジ型フォ)・レジスト6を感光させてい
る。
When FEB is used as a means for exposing the positive photoresist 6 as in the above embodiment, the conditions such as the type of ions to be implanted and the accelerating voltage are appropriately selected to expose the positive photoresist to the desired depth. This makes it possible to form a three-dimensional resist profile. By utilizing this effect, the method according to this embodiment is shown in FIG. 1(b).
In the process shown in FIG. 1, first, the positive photoresist 1-6 of the part that is to become the bridge-like shape of the air bridge is exposed to light, and then in the step shown in FIG. The positive photoresist 6 in the desired area is exposed to light.

なお、上記実施例では、第1図(c)の工程で、第1図
(b)より加速電圧を高くしたFIBを用いたが、FI
Bの加速電圧を一定にして第1図(C)の工程のFIB
に用いるイオン種の質量数が、第1図(b)のFIBに
用いるイオン種の質量数より小さくなるように(例えば
第1図(b)の工程でSiイオン、第1図(C’lの工
程でBeイオンを用いる)、それぞれの工程のFIBに
用いるイオン種を選んでやっても同様な作用がある。た
だし、この場合第1図(C)の工程で、FIBがポジ型
フ士トレジスト6をGaAs基板1との界面に至るまで
感光させるように加速電圧を選んでやることが必要であ
る。また以上あげた例では、第1図(c)の工程にFI
B感光を用いたが、光学露光,EB露光,X線露光等ポ
ジ型フォトレジスト6をGaAs基板1との界面に至る
まで感光させることができろものであれば何でもよい。
In the above example, in the step of FIG. 1(c), an FIB with a higher acceleration voltage than that of FIG. 1(b) was used;
FIB in the process of Figure 1 (C) with the acceleration voltage of B constant.
The mass number of the ion species used for FIB is smaller than the mass number of the ion species used for FIB in FIG. (Be ions are used in the process shown in Figure 1 (C)), the same effect can be obtained by selecting the ion species used in the FIB in each process.However, in this case, in the process shown in Figure 1 (C), the FIB is It is necessary to select an accelerating voltage so as to expose the photoresist 6 to the interface with the GaAs substrate 1.In addition, in the example given above, FI is added to the process shown in FIG. 1(c).
Although B exposure was used, any exposure method such as optical exposure, EB exposure, or X-ray exposure may be used as long as it can expose the positive photoresist 6 to the interface with the GaAs substrate 1.

〔発明の効果〕〔Effect of the invention〕

この発明は以上説明したとおり、所要数の電極が形成さ
れた半導体基板上にフォトレジスト較的厚く塗布する工
程,半導体基板の少なくとも2つの電極を綿状に結ぶ範
囲のフォトレジスト1回目の露光で所定深さを露光する
工程,各電極上のフォトレジストを2回目の露光で電極
界面まで露光する工程,現像後各露光部分を除去して立
体的しンストプロファイルを形成する工程,この立体的
レレストプロファイルを有するレジストパターンをマス
クとして金属蒸着により蒸着金属層を形成する工程,リ
フトオフにより残ったフォトレジスト アブリッジを形成する工程とからなるので、従来に比へ
て少ない工程数でエアブリッジを形成できる。特に、写
真製版のマスク合せの繰り返しが誠ることからアライメ
ント精度が上がり、形状の優れたエアブリッジを形成で
きるという効果がある。
As explained above, the present invention includes a step of coating a relatively thick layer of photoresist on a semiconductor substrate on which a required number of electrodes are formed, and a first exposure of the photoresist in an area connecting at least two electrodes of the semiconductor substrate in a cotton-like manner. A process of exposing the photoresist to a predetermined depth, a process of exposing the photoresist on each electrode to the electrode interface in a second exposure, a process of removing each exposed area after development to form a three-dimensional cast profile, and a process of forming a three-dimensional resist profile. Forming an air bridge in fewer steps than conventional methods, as it consists of a step of forming a vapor-deposited metal layer by metal vapor deposition using a resist pattern with a rest profile as a mask, and a step of forming a photoresist bridge remaining by lift-off. can. In particular, since the mask alignment in photolithography is repeated repeatedly, alignment accuracy is improved and an air bridge with an excellent shape can be formed.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)〜(f)はこの発明の一実施例による微細
パターン形成方法における主要製造工程を示す断面図、
第2図(a)〜(」)は従来の微細パターン形成方法の
主要工程を示す断面図である。 図において、1はGaAs基板、2は電極、6はポジ型
フォトレジスト スト感光部分、7は蒸着金属層である。 なお、各図中の同一符号は同一または相当部分を示す。 代理人 大 岩 増 雄   (外2名)第1r:!J 手続補正書(自発) 1、事件の表示   特願昭61−156545号2、
発明の名称   微細パターン形成方法3、補正をする
者 事件との関係  特許出願人 住 所    東京都千代田区丸の内二丁目2番3号。 名 称  (601)三菱電機株式会社代表者志岐守哉 4、代理人 住 所    東京都千代田区丸の内二丁目2番3号5
、補正の対象 明細書の発明の詳細な説明の欄および図面6、補正の内
容 (1)明細書第6頁20行、第7頁6〜7行の11、 
ox 103cm−2Jを、それぞれ「1.0×101
3cm−2Jと補正する。 (2)  同じく第6頁20行の「加圧」を、「加速」
と補正する。 (3)  同じく第7頁10行の「橋型のい状」を、「
橋状のい型」と補正する。 (匂 第1図を別紙のように補正する。 以  上 第1 +!JILIJLJII11 1:GaAs基板
FIGS. 1(a) to 1(f) are cross-sectional views showing main manufacturing steps in a fine pattern forming method according to an embodiment of the present invention;
FIGS. 2(a) to 2(a) are cross-sectional views showing the main steps of a conventional fine pattern forming method. In the figure, 1 is a GaAs substrate, 2 is an electrode, 6 is a positive photoresist photosensitive area, and 7 is a vapor deposited metal layer. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masuo Oiwa (2 others) 1st r:! J Procedural amendment (voluntary) 1. Indication of the case Patent application No. 156545/1982 2.
Title of the invention: Fine pattern formation method 3, relationship with the case of the person making the amendment Patent applicant address: 2-2-3 Marunouchi, Chiyoda-ku, Tokyo. Name (601) Mitsubishi Electric Corporation Representative Moriya Shiki 4, Agent Address 2-2-3-5 Marunouchi, Chiyoda-ku, Tokyo
, Detailed Description of the Invention column of the specification subject to amendment and Drawing 6, Contents of the amendment (1) Page 6, line 20 of the specification, page 7, lines 6-7, 11,
ox 103cm-2J, respectively “1.0×101
Correct it to 3cm-2J. (2) Similarly, on page 6, line 20, change “pressurization” to “acceleration”
and correct it. (3) Also, change the “bridge-shaped shape” on page 7, line 10 to “
Corrected as ``bridge-like type''. (Correct Figure 1 as shown in the attached sheet.

Claims (1)

【特許請求の範囲】[Claims] 半導体基板表面にエアブリッジを形成する工程において
、所要数の電極が形成された半導体基板表面にフォトレ
ジストを比較的厚く塗布する工程、前記半導体基板の少
なくとも2つの電極を線状に結ぶ範囲のフォトレジスト
を1回目の露光で所定の深さに露光する工程、前記各電
極の形成されている範囲のフォトレジストを2回目の露
光で電極界面まで露光する工程、二段階によって露光し
たレジスト露光部分を現像後除去し、立体的レジストプ
ロファイルを形成する工程、前記立体的レジストプロフ
ァイルを有するレジストパターンをマスクとして金属蒸
着を行い、蒸着金属層を形成する工程、リフトオフによ
り残ったフォトレジストとともに不要な蒸着金属層を除
去して、エアブリッジを形成する工程を含むことを特徴
とする微細パターン形成方法。
In the step of forming an air bridge on the surface of a semiconductor substrate, a step of applying a relatively thick photoresist to the surface of the semiconductor substrate on which a required number of electrodes have been formed, a step of applying photoresist to a region linearly connecting at least two electrodes of the semiconductor substrate; A step of exposing the resist to a predetermined depth in the first exposure, and a step of exposing the photoresist in the area where each electrode is formed up to the electrode interface in the second exposure. A process of removing after development to form a three-dimensional resist profile, a process of performing metal vapor deposition using the resist pattern having the three-dimensional resist profile as a mask to form a vapor-deposited metal layer, removing unnecessary vapor-deposited metal along with the photoresist remaining after lift-off. A method for forming a fine pattern, comprising the step of removing a layer to form an air bridge.
JP15654586A 1986-07-02 1986-07-02 Minute pattern forming method Pending JPS6312156A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15654586A JPS6312156A (en) 1986-07-02 1986-07-02 Minute pattern forming method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15654586A JPS6312156A (en) 1986-07-02 1986-07-02 Minute pattern forming method

Publications (1)

Publication Number Publication Date
JPS6312156A true JPS6312156A (en) 1988-01-19

Family

ID=15630138

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15654586A Pending JPS6312156A (en) 1986-07-02 1986-07-02 Minute pattern forming method

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02219256A (en) * 1989-02-20 1990-08-31 Rohm Co Ltd Manufacture of air bridge wiring
JPH03126247A (en) * 1989-10-12 1991-05-29 Rohm Co Ltd Manufacture of semiconductor device
JPH0761344A (en) * 1993-08-24 1995-03-07 Central Jidosha Kk Brake air bleeding device for vehicle
US5468595A (en) * 1993-01-29 1995-11-21 Electron Vision Corporation Method for three-dimensional control of solubility properties of resist layers
US7714235B1 (en) 1997-05-06 2010-05-11 Formfactor, Inc. Lithographically defined microelectronic contact structures

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61251149A (en) * 1985-04-30 1986-11-08 Fujitsu Ltd Manufacture of semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61251149A (en) * 1985-04-30 1986-11-08 Fujitsu Ltd Manufacture of semiconductor device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02219256A (en) * 1989-02-20 1990-08-31 Rohm Co Ltd Manufacture of air bridge wiring
JPH03126247A (en) * 1989-10-12 1991-05-29 Rohm Co Ltd Manufacture of semiconductor device
US5468595A (en) * 1993-01-29 1995-11-21 Electron Vision Corporation Method for three-dimensional control of solubility properties of resist layers
JPH0761344A (en) * 1993-08-24 1995-03-07 Central Jidosha Kk Brake air bleeding device for vehicle
US7714235B1 (en) 1997-05-06 2010-05-11 Formfactor, Inc. Lithographically defined microelectronic contact structures

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