JPS63121305A - Automatic gain control circuit - Google Patents

Abstract

PURPOSE:To set a level with a small number of transistors and to facilitate the integration of a circuit by charging a capacity element with first and second circuits which are connected to a gain control circuit and a current mirror circuit and feeding back the charging charge to the gain control circuit. CONSTITUTION:One of differential outputs from the gain control circuit G is inputted in the common base of T1 and T2 which are the transistors TR of the first circuit obtained by connecting m-number of transistors (TR) in parallel and the other output is inputted in the base of T3 which is the TR of the second circuit obtained by connecting n-number of TRs in parallel. The first circuit is connected to the bias side of the current mirror circuit consisting of a diode D and a TR T4 and the second circuit is connected to the output side of the current mirror circuit. To the connecting point between the mirror circuit and the second circuit, a control TR T5 is connected and the capacity element C is charged with the output according to the current on the output side of the mirror circuit and the current flowing in the second circuit. And the charging charge is made to feed back to the circuit G in a specified time constant with a resistance R.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to automatic gain control circuits.

[Prior art] Conventionally, the generally used automatic gain control circuit
The configuration is as shown in the figure. Since each output of the differential output type gain control circuit G cannot be directly supplied to the comparator C, h' 4 has been completed.

To explain the operation, the output voltage v1 from the gain control circuit G is applied to the transistor T8. If the change in the lid current of transistor T and T when applied to the base of T7 is 11 and the bias current is 21, then
Currents of (I+i) and (1-i) flow through transistors T and T, respectively, and as a result, transistors T
The collector potential vc6 of the transistor T falls, and the collector potential vc7 of the transistor T rises, which is expressed as vc6slIvoc-R1(l+1) ■c7''''Vec-R2(1-i), and the comparison level is given by vc6''Vc7. Therefore, for example, if the resistance values of resistors R and R are set to 1:2, when the resistance value becomes i-1/3 or more, the transistor T6
The collector voltage of transistor T7 becomes lower than that of transistor T7, comparator C operates, and the output of gain control circuit G is fed back to become smaller.

Through this operation, the output of the gain control circuit is automatically controlled so that it becomes i-I/3.

[Problems to be Solved by the Invention] In the above circuit configuration, the level is set using the resistors R and H, which requires relative accuracy of each resistor, and is not suitable for integration.

Furthermore, since a level setting circuit and a comparator are required, the overall configuration becomes complicated.

The present invention simplifies the circuit configuration and provides a configuration suitable for integration.

[Means for solving the problem] The present invention provides one differential output from a gain control circuit to the bases of m (m=1.2...) parallel-connected transistors forming a first circuit. n (n=1.2..., however, n
≠ m) transistors connected in parallel, a first circuit is connected in series to the bias side of the current mirror circuit, and a second circuit is connected in series to the output side of the current mirror circuit.
The base of the control transistor is connected to the connection point between the current mirror circuit and the second circuit, and the charging voltage of the capacitor, which is charged by the output of the control transistor, is fed back to the gain control circuit. The differential output is controlled.

[Example] In FIG. 1, G is a gain control circuit that generates a differential output;
T and T2 are transistors forming the first circuit, T3 is a transistor forming the second circuit,
D and T4 are a diode and a transistor, respectively, forming a current mirror circuit.

T5 is a control transistor, C is a capacitive element, and the differential output of the gain control circuit G is controlled by the charging voltage thereof. R is a transistor for discharging the charge of the capacitive element C in an appropriate specific stage.

Next, the operation will be explained. First, transistor T
, T , T bias current is I, person 1 2
B The amount of change in the collector current of the transistors T and T due to the force signal is t s The amount of change in the collector current of the transistor T3 is 12. Therefore, the first
When a differential output as shown in the figure occurs, 2 (1-1) + (1+12) -31-2i is obtained from the basic characteristics of a differential amplifier circuit.
, +t2 cotton 0,', i 2-2 L.

becomes. Therefore, by applying an input signal, the collectors of transistors T and T are set to 2(1-11
) flows through the collector of the transistor T3, and a collector current (I + 2 s t ) flows through the collector of the transistor T3.

Since the diode D and the transistor T4 constitute a current mirror circuit, the collector of the transistor T has 2(I
11) and the current 'b5 flowing to the base of the transistor T5 is the difference between the collector current Ic3 of the transistor T3 and the collector current of the transistor T4, so Ib5-2 (1-t, ) - (1+
2 ii) l-4il.

When no input signal is applied (11-0), Ib
Since 5>0, the transistor T5 is in a cut-off state, but when an input signal is applied and 11 becomes larger than 1/4, the transistor T5 becomes active and a collector current flows through the transistor T5. Therefore, the charging voltage of the capacitive element C increases by -L, feedback is applied to the gain control circuit G, and its differential output decreases. If 11 becomes equal to 1/4 due to this decrease in the differential output, the transistor T
The base current Ib5 of 5 becomes 0, and the transistor T5 becomes cut-off. Therefore, the charge in the capacitor C is discharged through the resistor R, the feedback voltage to the gain control circuit G decreases, and its differential output increases.

By repeating the above operations, the i-knee is maintained at 1/4, and the gain is automatically controlled.

Note that in the above embodiment, two transistors are connected in parallel as the first circuit, and one transistor is used as the second circuit, but the present invention is not limited to this. The first circuit has m (m=1.2...) transistors connected in parallel, and the second circuit has n (n=1, 2-) transistors connected in parallel.
1, where m=Pn) transistors are connected in parallel, and the reference current 11 can be set to an arbitrary value by setting m and n.

That is, in the case of the above configuration, a current of (1-t l) flows through each of the m transistors of the first circuit, and a current of (1-t l) flows through the m transistors of the first circuit, and
Each transistor in the circuit has (1+ m i
Since a current of l/n) flows, the base current 'b5 of transistor T5 is l bs-m (l-11) -n (1+ m t
1/n)-(m-n)! -2m11. ■The reference current 11 that becomes b5” 0 is %11,
w (m-n)I/2m, and the level can be arbitrarily set by setting the number m and n of transistors.

[Effects of the Invention] According to the present invention, the circuit configuration is simpler than the conventional one, and the level can be set by the number of transistors, so high precision can be achieved by using transistors with the same characteristics, making it suitable for integration. become something.

[Brief explanation of the drawing]

FIG. 1 is an electric circuit diagram showing an embodiment of the present invention, and FIG. 2 is an electric circuit diagram showing an example of a conventional circuit configuration. G... Gain control circuit T, T2... First circuit T3... Second circuit, T4... Current mirror circuit T5... Control transistor C... Capacitive element R... More than resistance

Claims (1)

[Claims] A gain control circuit that generates a differential output for gain control, and m (m=1, 2...) transistors whose common base input is one output from this gain control circuit. n (n=1, 2...
, However, the second circuit is configured by connecting n≠m) transistors in parallel, and the first circuit is connected in series to the bias side of the current mirror circuit, and the second circuit is connected to the output side of the current mirror circuit. circuits are connected in series, and the base input side is connected to the connection point between the current mirror circuit and the second circuit, and the current flowing to the output side of the current mirror circuit and the current flowing to the second circuit are a control transistor that generates an output, a capacitive element charged by the output current of the control transistor, a resistive element that discharges the charge of the capacitive element at a predetermined time constant, and a charging voltage of the capacitive element An automatic gain control circuit characterized in that it feeds back to the gain control circuit to control its differential output.