JPS63116541A - Reception processing system - Google Patents

Abstract

PURPOSE:To set a direct memory access controller DMAC at a high speed at the time of receiving the data and to reduce a receiving unexpected omission and a receiving overrun by setting the head address of the buffer to be received and the maximum receiving data length to a register beforehand. CONSTITUTION:When the data are received, the head address of a buffer to store the data to be received next and the maximum receiving data length are automatically set from a register group 6 to the address register of a DMC5 and a byte counter register with the hardware, and the receiving interruption is applied. When the receiving interruption is applied, a high speed receiving processing program on a ROM 2 is activated. Thus, even to the receiving of the data string with a short receiving interval, the receiving unexpected omission, the receiving overrun, etc., can be reduced.

Description

[Detailed description of the invention] 〔Technical field〕 The invention relates to a reception processing method in data communication.

[Prior Art] Conventionally, a control deep that sends and receives data, a RAM that stores the sent and received data, and a direct memory access controller (that transfers data between the control deep and the RAM) has been used.
In the reception processing involved in data communication consisting of a DMAC (hereinafter referred to as DMAC), after one reception is completed, the DMAC settings for the next reception are directly performed by software during reception interrupt processing. For this reason, when receiving short consecutive data strings, the interrupt mask state may continue for a long time, and the DMAC setting by software may be delayed, causing reception dropouts, reception overruns, etc. There was a drawback.

(Purpose) The first objective of the invention is to solve the above problems and perform the Ukei 3 processing at high speed.

(Example) Hereinafter, the tree invention will be described in detail. FIG. 1 is a block diagram showing an embodiment of the tree invention, and FIG. 2 is a flowchart of high-speed reception processing.

In FIG. 1, 1 is an MPLI, 2 is a ROM that stores a high-speed reception processing program, 3 is a RAM that stores received data, and 4GJ data transmission/reception control deep (hereinafter referred to as A).
(denoted as DLC), 5 is the RAM and ADLC
The DMAC 16 that transfers data between the two is a register group that stores the next DMAC setting value, 7 is a read/write control circuit, 8 is a dip select control circuit, 9 is a sequence circuit, 10 is a start/stop control circuit, and 11 is a frame 12 is a bus arbiter, and 13 is an interrupt control circuit.

In this embodiment, as shown in FIG.
, initialize the DMAC 5, and set the start address and maximum received data length of the buffer in which the first received data on RAMa should be stored, respectively, to 71 of the DMAC 5.
~Set in the response register and hide counter register,
The start address and maximum received data length of the buffer for storing the second received data on the RAM 3 are set in the register group 6.

As step 2, when data is received, the start address and maximum received data length of the buffer in which the next received data is to be stored are transferred from the register group 6 to the DMA C5.
The address register and byte counter register are automatically set by hardware, and a reception interrupt is generated.

As step 3, when a reception interrupt occurs, ROM2
The above high-speed reception processing program is started. In the conventional method, the start address and maximum received data length of the buffer in which the next received data should be stored must be directly set in the address register and hide counter register of the DMAC5, but if Jl<1, the tree method Well then, bar)・
This process is not necessary because the data is automatically set to DMAC5 from the register 71T6 by the software. In other words, the high-speed reception program on the ROM 2 further secures a buffer in the RAM 3 to store the next data to be received, and writes the start address and maximum reception data length of the buffer to the register 11-6. Exclude interrupt processing (J).

Thereafter, steps 2 and 3 will be repeated.

As explained above, in the tree trunk configuration, the DMAC settings for the next reception, which were conventionally performed during reception interrupt processing, are automatically performed by software immediately after reception. Therefore, it is possible to reduce reception dropouts, reception overruns, etc. even when receiving data strings with short reception intervals.

In the above embodiment, the register group to be set in advance is one stage, but it is also possible to configure the register group to be n stages. In this case, if you set the DMAC and the n-stage register group during the initial setting in step 1, the set values of the register group will be automatically shifted by the hardware every time reception is received, and the software will automatically shift the set values of the register group to the n-stage register. You only need to set the group.

〔effect〕

As described above, according to the present invention, DMAC settings can be performed at high speed when receiving data, and reception dropouts and reception overruns can be reduced.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the reception processing circuit, and Fig. 2 is a flowchart of the reception processing circuit, where 1 is the MPU, 2 is the ROM, and 3
is a RAM, 4 is an ADLC, 5 is a DMAC 16 is a register group, 7 is a read/write control circuit, 8 is a chip select control circuit, 9 is a sequence circuit, 10 is a start/chip control circuit, 11 is a frame valid judgment circuit, 12 is a The bus arbiter 13 is an interrupt control circuit.

Claims (1)

[Claims] A reception processing method characterized in that by setting the start address of a buffer to be received and the maximum reception data length in a register in advance, the setting of a direct memory access controller at the time of next reception is performed by hardware.