JPS63114236A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS63114236A JPS63114236A JP26093686A JP26093686A JPS63114236A JP S63114236 A JPS63114236 A JP S63114236A JP 26093686 A JP26093686 A JP 26093686A JP 26093686 A JP26093686 A JP 26093686A JP S63114236 A JPS63114236 A JP S63114236A
- Authority
- JP
- Japan
- Prior art keywords
- film
- melting point
- high melting
- etching stopper
- hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 238000005530 etching Methods 0.000 claims abstract description 36
- 229910052751 metal Inorganic materials 0.000 claims abstract description 32
- 239000002184 metal Substances 0.000 claims abstract description 32
- 238000000034 method Methods 0.000 claims abstract description 32
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 26
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 26
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 17
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 16
- 239000010937 tungsten Substances 0.000 claims abstract description 16
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 14
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 14
- 239000010410 layer Substances 0.000 claims abstract description 14
- 239000011229 interlayer Substances 0.000 claims abstract description 10
- 229910000838 Al alloy Inorganic materials 0.000 claims abstract description 8
- 230000008018 melting Effects 0.000 claims description 42
- 238000002844 melting Methods 0.000 claims description 42
- 230000007423 decrease Effects 0.000 abstract description 2
- 239000000463 material Substances 0.000 description 9
- 238000004544 sputter deposition Methods 0.000 description 6
- 238000006243 chemical reaction Methods 0.000 description 4
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910016570 AlCu Inorganic materials 0.000 description 1
- 229910000789 Aluminium-silicon alloy Inorganic materials 0.000 description 1
- 229910020968 MoSi2 Inorganic materials 0.000 description 1
- 229910008479 TiSi2 Inorganic materials 0.000 description 1
- 229910008814 WSi2 Inorganic materials 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- DFJQEGUNXWZVAH-UHFFFAOYSA-N bis($l^{2}-silanylidene)titanium Chemical compound [Si]=[Ti]=[Si] DFJQEGUNXWZVAH-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000009396 hybridization Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
(Jl要〕
本発明の半導体装置の製造方法は、アルミニウム又はア
ルミニウム合金からなる配線膜上に高融点シリサイド膜
又は高融点金1!膜を形成する工程と、高融点シリサイ
ド膜又は高融点金属膜上にエツチングストッパー膜を形
成する工程と、上記工程により形成された配線膜、高融
点シリサイド膜又は高融点金属膜、エツチングストッパ
ー膜の三層をエツチングして配線パターンを形成する工
程と、前記三層を層間絶縁膜で覆った後、前記エツチン
グストツバ−膜に達するスルーホールを形成する工程と
、前記エツチングストッパー膜を除去する工程と、スル
ーホールをCVDメタル法によりタングステンで埋め込
む工程とを有することを特徴としている。Detailed Description of the Invention (Required Jl) The method for manufacturing a semiconductor device of the present invention includes the steps of forming a high melting point silicide film or a high melting point gold 1! film on a wiring film made of aluminum or an aluminum alloy; A step of forming an etching stopper film on the silicide film or high melting point metal film, and etching the three layers of the wiring film formed by the above steps, the high melting point silicide film or high melting point metal film, and the etching stopper film to form a wiring pattern. a step of forming a through hole reaching the etching stopper film after covering the three layers with an interlayer insulating film; a step of removing the etching stopper film; and a step of forming the through hole by a CVD metal method. It is characterized by having a process of embedding with tungsten.
このようにCVDメタル法によりタングステンでスルー
ホールを埋め込むことによりカバレージに優れ、またア
ルミニウム膜上に高融点シリサイド膜又は高融点金属膜
を設けることによりコンタクト抵抗の低い半導体装置を
製造することができる。By filling the through holes with tungsten using the CVD metal method in this way, it is possible to manufacture a semiconductor device with excellent coverage and low contact resistance by providing a high melting point silicide film or a high melting point metal film on the aluminum film.
本発明は半導体装置の製造方法に関するものであり、更
に詳しく言えばアルミニウム膜上に高融点シリサイド膜
又は高融点金属膜を有し、タングステンで埋め込まれた
構造のスルーホールを有する半導体装置の製造方法に関
するものである。The present invention relates to a method for manufacturing a semiconductor device, and more specifically, a method for manufacturing a semiconductor device that has a high melting point silicide film or a high melting point metal film on an aluminum film and has a through hole with a structure filled with tungsten. It is related to.
従来スルーホールを埋め込む方法としては垂直蒸着法、
バイアススパッタ法、CVDメタル法が知られている。Conventional methods for filling through holes include vertical evaporation,
Bias sputtering method and CVD metal method are known.
いずれの方法によっても、配線層間が導通されれば所期
の目的が達成されるが、カバレージが悪い場合には信頼
性が低下する。半導体装置の微細化、高集積化に伴いス
ルーホールの大きさも輻2pm以下、あるいは17tm
以下と小さくなっている昨今においては、スルーホール
の埋め込み技術は装置の信頼性を左右する重要なもので
ある。In either method, the intended purpose is achieved as long as the wiring layers are electrically connected; however, if coverage is poor, reliability decreases. With the miniaturization and higher integration of semiconductor devices, the size of through holes has become smaller than 2 pm or 17 tm.
Nowadays, as devices become smaller and smaller, through-hole embedding technology is important as it affects the reliability of devices.
上記埋め込み方法のうち、垂直蒸着法はカバレージの点
でスバフタ法より優れるが、材料として合金は使えない
欠点がある。また、バイアススパッタ法は、合金も材料
として使用することができるが、カバレージが悪く、ま
たスパッタ時に温度400℃程度、DC200V程度の
条件にするため、例えばスパッタ材料のアルミニウムと
シリコン基板との間に反応がおこるなどの欠点がある。Among the above-mentioned embedding methods, the vertical evaporation method is superior to the suvafuta method in terms of coverage, but has the disadvantage that alloys cannot be used as the material. Bias sputtering can also use alloys as materials, but the coverage is poor and the sputtering conditions are about 400°C and about 200V DC, so for example, there is a gap between aluminum, which is the sputtering material, and the silicon substrate. There are disadvantages such as reactions.
一方、CVDメタル法のうち選択的成長を行うことがで
きる方法は、微細なスルーホールの埋め込み方法として
有用である。アルミニウムやシリコン上に選択的成長を
行なえるタングステンが現在知られている選択的成長回
旋なCVDメタル法に適用しうる唯一の材料である。On the other hand, among the CVD metal methods, a method that allows selective growth is useful as a method for burying fine through holes. Tungsten, which can be grown selectively on aluminum and silicon, is the only material currently known that can be applied to the selectively grown CVD metal process.
このタングステンを用いるCVDメタル法は、WF6を
用イテアルミニウムやAlSi、AlCuなどの合金上
にタングステンを成長させる方法である。この方法によ
ればスルーホールを埋め込むことができるが、抵抗の高
いAuFがアルミニウム層とタングステン層の界面に生
じてしまう、コンタクト抵抗を低下させるためにはWS
i 、 TiSi2*MoSi2など低抵抗、高融点
のシリサイド上にタングステンを成長させればシリサイ
ドの保1[となり、Anと−F6の反応を防止すること
ができる。This CVD metal method using tungsten is a method in which tungsten is grown on an alloy such as aluminum, AlSi, or AlCu using WF6. Although this method allows through-holes to be filled, AuF with high resistance is generated at the interface between the aluminum layer and the tungsten layer.
If tungsten is grown on a silicide with low resistance and high melting point, such as TiSi2*MoSi2, it will act as a silicide and prevent the reaction between An and -F6.
しかし、アルミニウム層上に高融点シリサイド膜又は高
融点金属膜を形成しただけでは、スルーホール形成のた
めに通常用いられるフレオン系のガスによって高融点シ
リサイド膜又は高融点金属膜までエツチングされ、A交
F形成防止の機渣を果たし得ない。However, if only a high melting point silicide film or a high melting point metal film is formed on the aluminum layer, the high melting point silicide film or high melting point metal film will be etched by the Freon gas normally used to form through holes, and the A It cannot function as a means to prevent F formation.
本発明はかかる点に鑑みて創作されたものであり、スル
ーホールのコンタクト抵抗が小さく、カバレージ性に優
れる信頼性の高い半導体装置の提供を目的とする。The present invention was created in view of these points, and aims to provide a highly reliable semiconductor device with low through-hole contact resistance and excellent coverage.
本発明は、アルミニウム又はアルミニウム合金からなる
配線膜上に高融点シリサイド膜又は高融点金属膜を形成
する工程と、高融点シリサイド膜又は高融点金属膜−ヒ
にエツチングストッパー膜を形成する工程と、上記工程
により形成された配線膜、高融点シリサイド膜又は高融
点金属膜、エツチングストッパー膜の三層をエツチング
して配線パターンを形成する工程と、前記三層を層間絶
縁1模で覆った後、前記エツチングストッパー膜に達す
るスルーホールを形成する工程と、前記エツチングスト
ッパー膜を除去する工程と、スルーホールをCVDメタ
ル法によりタングステンで埋め込む工程とを有すること
を特徴とする。The present invention includes a step of forming a high melting point silicide film or a high melting point metal film on a wiring film made of aluminum or an aluminum alloy, and a step of forming an etching stopper film on the high melting point silicide film or high melting point metal film. A step of etching the three layers of the wiring film, high melting point silicide film or high melting point metal film, and etching stopper film formed in the above steps to form a wiring pattern, and after covering the three layers with an interlayer insulation layer, The method is characterized by comprising a step of forming a through hole reaching the etching stopper film, a step of removing the etching stopper film, and a step of filling the through hole with tungsten by a CVD metal method.
前記高融点シリサイド膜又は高融点金J、1m膜は、W
F6 と配線膜材料のAn 、 AM−9i、 AM
−Cuなどのアルミニウム合金とが反応してAuFの生
成が防止できれば良く、膜厚は500〜100OAが適
当である。The high melting point silicide film or high melting point gold J, 1m film is W
F6 and wiring film material An, AM-9i, AM
It is sufficient that the formation of AuF due to reaction with aluminum alloys such as -Cu can be prevented, and the appropriate film thickness is 500 to 100 OA.
エツチングストッパー膜は居間絶縁膜のエツチングによ
るスルーホール形成時に同時にエツチングされないよう
な材料、すなわち、居間絶縁膜材料とエツチング選択比
の異なる材料であることが必要である0層間絶縁膜をP
・SGで形成する場合には、エツチングストッパー膜材
料は例えばA!;L、 A11−Si、 An−Cuな
どのアルミニウム合金が望ましい。The etching stopper film must be made of a material that is not etched at the same time when through-holes are formed by etching the living room insulating film, that is, a material that has a different etching selectivity from the living room insulating film material.
- When forming with SG, the etching stopper film material is A!, for example. Aluminum alloys such as L, A11-Si, and An-Cu are desirable.
本発明の半導体装22製造方法によれば、高融点シリサ
イド膜又は高融点金属膜上に層間絶縁膜とエツチング選
択比の異なるエツチングストッパー膜を形成するので、
層間絶縁膜にエツチングによるスルーホール形成時にシ
リサイドまでエツチングされることがない。According to the method for manufacturing the semiconductor device 22 of the present invention, an etching stopper film having a different etching selectivity from the interlayer insulating film is formed on the high melting point silicide film or the high melting point metal film.
When forming through holes in the interlayer insulating film by etching, the silicide is not etched.
また層間絶縁膜のエツチング後に、上記エツチングスト
ッパー膜をエツチングして除いたのち、タングステンで
スルーホールを埋め込む、このときタングステンは高融
点シリサイド膜又は高融点金属膜上に成長するのでコン
タクト抵抗を高くするAJIFの生成を防止することが
できる。After etching the interlayer insulating film, the etching stopper film is etched away, and the through holes are filled with tungsten. At this time, tungsten grows on the high melting point silicide film or the high melting point metal film, increasing the contact resistance. Generation of AJIF can be prevented.
次に図を参照しながら本発明の実施例について説明する
。第1図(a)〜(e)は本発明の実施例に係る半導体
装置の製造方法を説明する図である。Next, embodiments of the present invention will be described with reference to the drawings. FIGS. 1(a) to 1(e) are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.
(1)ilfJ1図(a)において、■はSi基板、2
は熱酸化又はCVDによって形成された5iOzW2で
ある。5i02膜2上にA交配線膜3を0.87zm厚
。(1) In ilfJ1 diagram (a), ■ is a Si substrate, 2
is 5iOzW2 formed by thermal oxidation or CVD. A hybridization line film 3 with a thickness of 0.87 zm is placed on the 5i02 film 2.
WSi2で高融点シリサイド膜又は高融点金属膜4を7
0OA厚、 A 1−5iでエツチングストッパー膜5
をIGOOA厚に連続スパッタ法で形成する。High melting point silicide film or high melting point metal film 4 is made of WSi2.
Etching stopper film 5 with 0OA thickness and A 1-5i
is formed to a thickness of IGOOA by continuous sputtering.
(2)次に配線パターンに従って配m膜3.高融点シリ
サイド膜又は高融点金8114.エツチングストッパー
膜5の3層を順次C見−系、フレオン系、C1−系の反
応性イオンエツチングによりエツチングする(第1図(
b))。(2) Next, according to the wiring pattern, 3. High melting point silicide film or high melting point gold 8114. The three layers of the etching stopper film 5 are sequentially etched by C-based, Freon-based, and C1-based reactive ion etching (see Fig. 1).
b)).
(3)CVDによってPSG層間絶縁膜6を成長させる
(第1図(C)) 、なお、SiO系樹脂で平坦化も行
う。(3) The PSG interlayer insulating film 6 is grown by CVD (FIG. 1(C)), and planarization is also performed using a SiO-based resin.
(0レジストマスクで7レオン系ガスの反応性イオンエ
ツチングによりエッチレグストッパー膜5に達するスル
ーホールを形成する(第1図(d))。(A through hole reaching the etch leg stopper film 5 is formed by reactive ion etching using a 7 Leon type gas using a 0 resist mask (FIG. 1(d)).
(5)次にWの選択成長前処理としてC交 系のプラズ
マエツチングを行って工程(4)で形成したスルーホー
ル下のエツチングストッパー膜5を除去し、その後M続
してWF6ガスを用いてCVDメタル法によりスルーホ
ール中にWW2を成長させる(第1図(e) ) 。(5) Next, as a pretreatment for selective growth of W, C-cross plasma etching is performed to remove the etching stopper film 5 under the through-hole formed in step (4), and then WF6 gas is used for etching. WW2 is grown in the through hole by the CVD metal method (FIG. 1(e)).
なおエツチングストッパー膜5の除去は、リン酸、アル
カリ水溶液などによるウェット・エツチング、CVDの
前処理としてCVD装置の中でプラズマによるエツチン
グで行ってもよい。Note that the etching stopper film 5 may be removed by wet etching using phosphoric acid, alkaline aqueous solution, or the like, or by etching using plasma in a CVD apparatus as a pretreatment for CVD.
(6)つづいて第2配!a膜としてA文を0.81Lm
厚にスパッタ法にスパッタ法により形成する。(6) Next up is the second prize! 0.81Lm for A sentence as a film
It is formed thickly by sputtering.
本発明の実施例のコンタクト抵抗は1O−9〜10−8
Ωcm2であり、高融点シリサイド膜又は高融点金属膜
4.エツチングストー/パー膜5を形成しない他は実施
例と同様の工程により形成した従来例のコンタクト抵抗
は1O−1Ocm?であった。The contact resistance of the embodiment of the present invention is 1O-9 to 10-8
Ωcm2, high melting point silicide film or high melting point metal film4. The contact resistance of the conventional example, which was formed by the same process as the example except that the etching stopper film 5 was not formed, was 1O-1Ocm? Met.
以1のように本発明の半導体装lの製造方法によれば、
CVDメタル法によってスルーホールのタングステン埋
め込みを行うので、カバレージ性が良好となり、コンタ
クト抵抗も低くなる。According to the method for manufacturing a semiconductor device 1 of the present invention as described in 1 below,
Since the through holes are filled with tungsten using the CVD metal method, coverage is good and contact resistance is low.
本発明によればAnと−F6が反応しコンタクト抵抗を
高くするAiFが生成するのを高融点シリサイド膜又は
高融点金属膜によって防ILするため、スルーホールを
アルミニウム又はアルミニウム合金で埋めた場合とほぼ
同等の低コンタクト抵抗となる。According to the present invention, in order to prevent IL from forming AiF, which increases contact resistance due to the reaction between An and -F6, by using a high melting point silicide film or a high melting point metal film, it is possible to prevent the through hole from being filled with aluminum or an aluminum alloy. Almost the same low contact resistance.
更に、アルミニウム蒸着をはじめとする他のスルーホー
ル埋め込み方法によっては得られない優れたカバレージ
性をCVD法によって保証することができる。Furthermore, the CVD method can ensure excellent coverage that cannot be obtained by other through-hole filling methods such as aluminum vapor deposition.
以上本発明の方法で製造した半導体装置は信頼性、高速
応答性に優れる。The semiconductor device manufactured by the method of the present invention has excellent reliability and high-speed response.
第1図(a)〜(e)は本発明の実施例に係る半導体装
置の製造方法を説明する断面図である。
(符号の説明)
1・・・SI大基板
2・・・5i02膜、
3・・・人文配線膜、
4・・・高融点シリサイド膜又は高融点金属膜、5・・
・エツチングストッパー膜、
6・・・PSG層間絶縁膜、
7・・・タングステンで埋め込んだスルーホール。FIGS. 1(a) to 1(e) are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention. (Explanation of symbols) 1... SI large substrate 2... 5i02 film, 3... Humanities wiring film, 4... High melting point silicide film or high melting point metal film, 5...
- Etching stopper film, 6...PSG interlayer insulating film, 7...Through hole filled with tungsten.
Claims (2)
膜上に高融点シリサイド膜又は高融点金属膜を形成する
工程と、 前記高融点シリサイド膜又は高融点金属膜上にエッチン
グストッパー膜を形成する工程と、上記工程により形成
された配線膜、高融点シリサイド膜又は高融点金属膜、
エッチングストッパー膜の三層をエッチングして配線パ
ターンを形成する工程と、 前記三層を層間絶縁膜で覆った後、前記エッチングスト
ッパー膜に達するスルーホールを形成する工程と、 前記エッチングストッパー膜を除去する工程と、 スルーホールをCVDメタル法によりタングステンで埋
め込む工程とを有することを特徴とする半導体装置の製
造方法。(1) A step of forming a high melting point silicide film or a high melting point metal film on a wiring film made of aluminum or an aluminum alloy, a step of forming an etching stopper film on the high melting point silicide film or a high melting point metal film, and the above steps. Wiring film, high melting point silicide film or high melting point metal film formed by process,
a step of etching three layers of an etching stopper film to form a wiring pattern; a step of forming a through hole reaching the etching stopper film after covering the three layers with an interlayer insulating film; and removing the etching stopper film. 1. A method for manufacturing a semiconductor device, comprising: a step of filling the through hole with tungsten by a CVD metal method.
ッパー膜がアルミニウム又はアルミニウム合金であるこ
とを特徴とする特許請求の範囲第1項記載の半導体装置
の製造方法。(2) The method of manufacturing a semiconductor device according to claim 1, wherein the interlayer insulating film is PSG, and the etching stopper film is aluminum or an aluminum alloy.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP26093686A JPH0691090B2 (en) | 1986-10-31 | 1986-10-31 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP26093686A JPH0691090B2 (en) | 1986-10-31 | 1986-10-31 | Method for manufacturing semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS63114236A true JPS63114236A (en) | 1988-05-19 |
JPH0691090B2 JPH0691090B2 (en) | 1994-11-14 |
Family
ID=17354828
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP26093686A Expired - Fee Related JPH0691090B2 (en) | 1986-10-31 | 1986-10-31 | Method for manufacturing semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0691090B2 (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4943539A (en) * | 1989-05-09 | 1990-07-24 | Motorola, Inc. | Process for making a multilayer metallization structure |
JPH039522A (en) * | 1989-06-07 | 1991-01-17 | Nec Corp | Manufacture of semiconductor device |
KR19990055768A (en) * | 1997-12-27 | 1999-07-15 | 김영환 | Manufacturing method of semiconductor device |
KR100365936B1 (en) * | 1995-12-20 | 2003-03-03 | 주식회사 하이닉스반도체 | Method for forming via contact in semiconductor device |
US6699777B2 (en) * | 2001-10-04 | 2004-03-02 | Micron Technology, Inc. | Etch stop layer in poly-metal structures |
US7508075B2 (en) | 2003-08-01 | 2009-03-24 | Micron Technology, Inc. | Self-aligned poly-metal structures |
-
1986
- 1986-10-31 JP JP26093686A patent/JPH0691090B2/en not_active Expired - Fee Related
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4943539A (en) * | 1989-05-09 | 1990-07-24 | Motorola, Inc. | Process for making a multilayer metallization structure |
JPH039522A (en) * | 1989-06-07 | 1991-01-17 | Nec Corp | Manufacture of semiconductor device |
KR100365936B1 (en) * | 1995-12-20 | 2003-03-03 | 주식회사 하이닉스반도체 | Method for forming via contact in semiconductor device |
KR19990055768A (en) * | 1997-12-27 | 1999-07-15 | 김영환 | Manufacturing method of semiconductor device |
US6699777B2 (en) * | 2001-10-04 | 2004-03-02 | Micron Technology, Inc. | Etch stop layer in poly-metal structures |
US6875679B2 (en) | 2001-10-04 | 2005-04-05 | Micron Technology, Inc. | Etch stop layer in poly-metal structures |
US7078327B2 (en) | 2001-10-04 | 2006-07-18 | Micron Technology, Inc. | Self-aligned poly-metal structures |
US7094673B2 (en) | 2001-10-04 | 2006-08-22 | Micron Technology, Inc. | Etch stop layer in poly-metal structures |
US7166527B2 (en) | 2001-10-04 | 2007-01-23 | Micron Technology, Inc. | Etch stop layer in poly-metal structures |
US7508074B2 (en) | 2001-10-04 | 2009-03-24 | Micron Technology, Inc. | Etch stop layer in poly-metal structures |
US7508075B2 (en) | 2003-08-01 | 2009-03-24 | Micron Technology, Inc. | Self-aligned poly-metal structures |
Also Published As
Publication number | Publication date |
---|---|
JPH0691090B2 (en) | 1994-11-14 |
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