JPS63111513A - Digital phase locked loop circuit - Google Patents
Digital phase locked loop circuitInfo
- Publication number
- JPS63111513A JPS63111513A JP61257243A JP25724386A JPS63111513A JP S63111513 A JPS63111513 A JP S63111513A JP 61257243 A JP61257243 A JP 61257243A JP 25724386 A JP25724386 A JP 25724386A JP S63111513 A JPS63111513 A JP S63111513A
- Authority
- JP
- Japan
- Prior art keywords
- phase
- frequency
- circuit
- comparator
- locked loop
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000003247 decreasing Effects 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
- H02P23/00—Arrangements or methods for the control of AC motors characterised by a control method other than vector control
- H02P23/18—Controlling the angular speed together with angular position or phase
- H02P23/186—Controlling the angular speed together with angular position or phase of one shaft by controlling the prime mover
Abstract
PURPOSE:To accurately keep frequency and phase by providing an automatic phase shifting circuit which switches and selects the outputs of a ring counter by a frequency control signal obtaining the phase difference signal received from a phase comparator through a loop filter. CONSTITUTION:Such a digital phase locked loop circuit consists of a phase comparator 1, a loop filter 2, an m-notation ring counter 3 and an automatic phase shift circuit 4. The value obtained by integrating the phase difference signal outputted from the comparator 1 via a filter 2 is turned into a frequency control signal and supplied to the circuit 4. Thus the frequency of a clock K is kept at a constant level. The circuit 4 shifts phase so that the frequency of the clock K is increased with a phase delay of the phase difference signal and decreased with a phase advance, respectively. Thus it is possible to accurately keep the frequency and the phase of an input signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61257243A JPS63111513A (en) | 1986-10-29 | 1986-10-29 | Digital phase locked loop circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61257243A JPS63111513A (en) | 1986-10-29 | 1986-10-29 | Digital phase locked loop circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63111513A true JPS63111513A (en) | 1988-05-16 |
Family
ID=17303676
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61257243A Pending JPS63111513A (en) | 1986-10-29 | 1986-10-29 | Digital phase locked loop circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63111513A (en) |
-
1986
- 1986-10-29 JP JP61257243A patent/JPS63111513A/en active Pending
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