JPS63107893U - - Google Patents

Description

[Brief explanation of the drawing]

Fig. 1... Conventional oscillation circuit, Fig. 2... An embodiment according to the present invention, Fig. 3... Fig. 2 Frequency dividing stages 7, 8
Output logic state table, FIG. 4...Example of a circuit for coarse adjustment. 1... Variable capacitor, 2... Oscillation inverter, 3... Crystal resonator, 4... Capacitor, 5... Oscillation circuit, 6... 1/2 frequency dividing circuit, 7...
...1/2 frequency divider circuit with set terminal, 8...1/2 frequency divider circuit with reset terminal, 9...N stage frequency divider circuit, 1
0...Detection circuit, 11, 12, 13...Setting terminal, 14...Latch circuit, 15, 16, 17, 18
...AND gate, 19, 20, 21, 22, 2
3...Setting terminal, 24...1/2 frequency divider circuit with set/reset terminal, 25...Detection circuit, 26...
Latch circuit, 27, 30, 31, 32...AND
Gate, 28, 29...AND-OR gate. Fig. 5a...Example when the state of the setting terminal is converted into a code, Fig. 5b...Truth table for the code conversion of Fig. 5a, Fig. 6...Setting by rotary switch An example of determining the terminal state. 33...Code conversion circuit, 34...Rotary switch. Figure 7: An example of a 1/2 frequency divider circuit with a set terminal. 35...Clocked inverter, 36...N
OR gate, 37...inverter.

Amendment May 22, 1982 The scope of claims for utility model registration is amended as follows.

[Claims for Utility Model Registration] An oscillation circuit that outputs a time reference signal , a frequency dividing circuit comprising a plurality of frequency division stages that divides the frequency of the time reference signal output from the oscillation circuit , and In an electronic timepiece that drives a timekeeping mechanism by an output signal from a frequency dividing circuit, at least two or more first frequency dividing stages having a preset mechanism among the frequency dividing circuits; a second frequency dividing stage comprising a larger number of frequency dividing stages and having a preset mechanism; a first frequency dividing stage that sets the first frequency dividing stage in a leading direction or a backward state and setting coarse adjustment data to be preset; a setting terminal, a second setting terminal for setting the second frequency division stage in a forward direction or a delay direction and setting fine adjustment data to be preset; a second setting terminal for setting the fine adjustment data to be preset ; The circuit enters a detection signal waiting state, detects the state of the logic φ of the first frequency dividing stage or the second frequency dividing stage preset in the frequency dividing circuit in the detection signal waiting state, and detects the state of the logic φ of the first frequency dividing stage or the second frequency dividing stage, a detection circuit that outputs a detection output signal from the detection circuit, and sets the first frequency division stage to a leading state or a delayed state by the first detection output signal from the detection circuit, and sets the coarse adjustment data to be preset to the above-mentioned coarse adjustment data. a first gate means for writing into a first frequency dividing stage; and a first gate means for setting the second frequency dividing stage in a leading direction state or a retarded state state by means of the second detection output signal from the detecting circuit and presetting the second frequency dividing stage; An electronic timepiece comprising second gate means for writing fine adjustment data into the second frequency dividing stage . The brief description of the drawing has been amended as follows. Page 9, line 6 of the specification: “An embodiment of the present invention”
The text has been corrected to read "a circuit diagram for explaining the present invention." On page 9, line 8 of the specification, the phrase ``Embodiment of a circuit that performs coarse adjustment'' has been amended to read ``a circuit diagram showing a configuration in which coarse adjustment and fine adjustment can be independently adjusted, which is an embodiment of the present invention.'' do.

Claims (1)

[Scope of utility model registration request] an oscillation circuit for obtaining a time reference; a frequency division circuit including a plurality of frequency division stages for dividing the time reference signal outputted from the oscillation circuit; and an output signal of the frequency division circuit to drive a timekeeping mechanism. In the electronic timepiece, at least two or more frequency dividing stages of the frequency dividing circuit have a preset mechanism, a write control circuit for writing data to the frequency dividing stage having the preset mechanism, and a frequency dividing stage having the preset mechanism. A setting terminal is used to set data to preset the frequency dividing stage, and the output signal of the frequency dividing circuit causes the circuit to enter an initial state or a detection signal waiting state. An electronic device comprising: a detection circuit for detecting the state of logic φ of a frequency stage; and gate means for writing data for presetting the frequency division stage into the frequency division stage having the preset mechanism based on a detection output signal of the detection circuit. clock.