JPS6298620A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6298620A JPS6298620A JP23726585A JP23726585A JPS6298620A JP S6298620 A JPS6298620 A JP S6298620A JP 23726585 A JP23726585 A JP 23726585A JP 23726585 A JP23726585 A JP 23726585A JP S6298620 A JPS6298620 A JP S6298620A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor substrate
- film
- oxide film
- silicide film
- metal silicide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は半導体装置に係り5特に半導体基板に対し接合
特性の良好な金属硅化膜の形成方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a semiconductor device, and particularly relates to a method for forming a metal silicide film having good bonding properties to a semiconductor substrate.
半導体集積回路の微細化に伴う回路の寄生抵抗の増加を
抑えるため、拡散層へ金属硅化膜を形成し低抵抗化する
必要がある。In order to suppress the increase in parasitic resistance of circuits due to miniaturization of semiconductor integrated circuits, it is necessary to form a metal silicide film on the diffusion layer to lower the resistance.
この方法のひとつとして、第2図に示すような熱反応に
より金属26と半導体基板21とを反応させ金属硅化膜
24を形成する方法がある。ところが、この方法では、
拡散層23の接合深さを浅くできず、金属硅化膜24の
表面が荒れる等の問題がある。この問題を回避する方法
として第3図に示すように、化学気相成長法等により金
属硅化膜34を被着し、リソグラフィ法によりパターン
を形成する方法がある。ところが、この方法では金DC
硅化11!J 34と拡散層33との界面に自然酸化膜
等が介在し、接触抵抗の低い接合が得にくい。One method for this is to form a metal silicide film 24 by causing the metal 26 and the semiconductor substrate 21 to react through a thermal reaction as shown in FIG. However, with this method,
There is a problem that the junction depth of the diffusion layer 23 cannot be made shallow, and the surface of the metal silicide film 24 becomes rough. As a method of avoiding this problem, as shown in FIG. 3, there is a method of depositing a metal silicide film 34 by chemical vapor deposition or the like and forming a pattern by lithography. However, with this method, gold DC
Silica 11! A natural oxide film or the like is present at the interface between J 34 and the diffusion layer 33, making it difficult to obtain a bond with low contact resistance.
なお、これらの方法に関連するものには 特開昭59−
200418号、同59−94819号等が挙げられる
。For those related to these methods, please refer to Japanese Patent Application Laid-open No. 1983-
No. 200418, No. 59-94819, and the like.
本発明の目的は、化学気相成長法あるいは蒸着法により
形成した金Jρ(硅化膜と不純物拡散層との良好な接合
を提供することにある。An object of the present invention is to provide a good bond between a gold Jρ (silicide) film formed by chemical vapor deposition or vapor deposition and an impurity diffusion layer.
上記目的を達成するために、本発明では、化学気相成長
法等により形成した金属硅化膜を酸化させることにより
、金属硅化膜を半導体基板側へ食い込ませ、金属硅化膜
と半導体基板との界面を初期の半導体基板側へ形成する
ことを特徴としている。In order to achieve the above object, the present invention oxidizes a metal silicide film formed by a chemical vapor deposition method or the like to cause the metal silicide film to dig into the semiconductor substrate side, thereby forming an interface between the metal silicide film and the semiconductor substrate. is characterized in that it is formed on the initial semiconductor substrate side.
以下、本発明の一実施例を第1図により説明する。 An embodiment of the present invention will be described below with reference to FIG.
まず同図(a)に示すように、酸化膜2の一部を除去し
不純物拡散層3を露出させた後、図(b)に示すように
タングステンシリサイド(WSiz)膜4を化学気相成
長法あるいは蒸着法により半導体基板1の全面に被着す
る。次に、図(c)に示すようにタングステンシリサイ
ド膜4を、還元性のある水素(Hz) と水蒸気(H
20) の混合雰囲気中で例えば温度950℃で酸化
し酸化膜5を形成する。この場合、酸化膜5を形成する
シリコン(Si、)が拡散層3から供給されるため、タ
ングステンシリサイド4と拡散層3との界面は、酸化膜
5を形成する前よりも半導体基板1側へ形成される。First, as shown in Figure (a), a part of the oxide film 2 is removed to expose the impurity diffusion layer 3, and then a tungsten silicide (WSiz) film 4 is grown by chemical vapor deposition as shown in Figure (b). It is deposited on the entire surface of the semiconductor substrate 1 by a method or a vapor deposition method. Next, as shown in Figure (c), the tungsten silicide film 4 is heated with reducing hydrogen (Hz) and water vapor (H
20) The oxide film 5 is formed by oxidation at a temperature of, for example, 950° C. in a mixed atmosphere. In this case, since silicon (Si) forming the oxide film 5 is supplied from the diffusion layer 3, the interface between the tungsten silicide 4 and the diffusion layer 3 is closer to the semiconductor substrate 1 than before the oxide film 5 is formed. It is formed.
次に1図(d)に示すように、酸化膜5とタングステン
シリサイド4のパターン形成を、公知のリングラフィ技
術により行う。Next, as shown in FIG. 1(d), patterning of the oxide film 5 and tungsten silicide 4 is performed using a known phosphorography technique.
ここでは、金属硅化膜をタングステンシリサイドを例に
とり記述したが、他の金属硅化膜であるモリブテンシリ
サイド等についても可能である。Here, the metal silicide film is described using tungsten silicide as an example, but other metal silicide films such as molybdenum silicide can also be used.
また、拡散層3の形成は、金属硅化膜4巾へ不純物を混
ぜておき酸化膜5を形成すると同時に半導体基板1側へ
不純物を拡散させることにより形成することもできる。Further, the diffusion layer 3 can also be formed by mixing an impurity into the width of the metal silicide film 4, forming the oxide film 5, and simultaneously diffusing the impurity toward the semiconductor substrate 1 side.
本発明によれば、金属硅化膜と半導体基板との界面が、
初期の半導体基板内へ形成される。これにより、良好な
界面特性が得られ、電気特性の良好な接合が形成できる
。According to the present invention, the interface between the metal silicide film and the semiconductor substrate is
Formed into an initial semiconductor substrate. As a result, good interfacial properties can be obtained, and a bond with good electrical properties can be formed.
第1図は本発明の一実施例を示す形成工程断面図、第p
徊は従来の形成工程断面図である。
11.21.31・・・半導体基板、12,22゜32
・酸化膜、13,23.33・・・不純物拡散層、14
.24.34・・タングステンシリサイド膜、]5・・
酸化膜、26・・・タングステン膜。FIG. 1 is a sectional view of the forming process showing one embodiment of the present invention,
The figure is a cross-sectional view of a conventional forming process. 11.21.31...Semiconductor substrate, 12,22°32
・Oxide film, 13, 23. 33... Impurity diffusion layer, 14
.. 24.34...Tungsten silicide film, ]5...
Oxide film, 26... tungsten film.
Claims (1)
を形成する方法において、半導体基板上の絶縁膜の一部
を開孔し不純物拡散層を露出させる工程と、該半導体基
板上へ化学気相成長法あるいは蒸着法により金属硅化膜
を被着する工程と、該金属硅化膜を酸化し、該金属硅化
膜と該不純物拡散層との界面を、酸化前の位置より半導
体基板内部へ形成することを特徴とする半導体装置の製
造方法。A method for forming a bond between an impurity diffusion layer and a metal silicide film in a semiconductor device includes a step of opening a hole in a part of an insulating film on a semiconductor substrate to expose the impurity diffusion layer, and a step of chemical vapor deposition on the semiconductor substrate. A process of depositing a metal silicide film by a method or a vapor deposition method, oxidizing the metal silicide film, and forming an interface between the metal silicide film and the impurity diffusion layer into the semiconductor substrate from the position before oxidation. A method for manufacturing a featured semiconductor device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23726585A JPS6298620A (en) | 1985-10-25 | 1985-10-25 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23726585A JPS6298620A (en) | 1985-10-25 | 1985-10-25 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6298620A true JPS6298620A (en) | 1987-05-08 |
Family
ID=17012837
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP23726585A Pending JPS6298620A (en) | 1985-10-25 | 1985-10-25 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6298620A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6524928B1 (en) * | 1999-03-04 | 2003-02-25 | Fuji Electric Co., Ltd. | Semiconductor device and method for manufacturing the same |
-
1985
- 1985-10-25 JP JP23726585A patent/JPS6298620A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6524928B1 (en) * | 1999-03-04 | 2003-02-25 | Fuji Electric Co., Ltd. | Semiconductor device and method for manufacturing the same |
US6774454B2 (en) | 1999-03-04 | 2004-08-10 | Fuji Electric Co., Ltd. | Semiconductor device with an silicon insulator (SOI) substrate |
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