JPS6286974A - Deflecting distortion correcting circuit - Google Patents

Abstract

PURPOSE:To correct the deflecting distortion and to suppress the deflecting distortion to the range or below of the quantizing error due to the scanning line by reading successively the video signal written in the picture memory in accordance with the contents of the writing address memory from the picture memory as the data and outputting it toward the displaying device. CONSTITUTION:In a memory 18, the address of a picture memory 15 obtained from the raster shape is stored. The video signal inputted from an input terminal 19 is supplied to a picture memory 17, supplied to a synchronizing separating circuit 20, and the vertical and horizontal synchronizing signals are separated. By using the synchronizing signal as the time reference, the writing address of the picture memory 17 is outputted from a writing address memory 18, and the video signal is written into the desired address of the picture memory. The data come to be a barrel shape which is complementary to the raster distortion shape, on the picture memory. At the time of reading, the data are read by the static column mode.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a deflection distortion correction circuit in a display device using a cathode ray tube, such as a television receiver.

[Background of the invention]

Distortion correction circuits in display devices using cathode ray tubes, such as conventional television receivers, have a problem in that residual distortion occurs. The problems will be explained below using drawings.

Since the phosphor screen of a cathode ray tube is almost flat, the rask shape without deflection distortion correction is as shown in Figure 2.
A left and right pincushion appears. In order to correct this, conventionally, a distortion correction current was passed through the deflection yoke.

FIG. 3 shows a specific example of a conventional deflection distortion correction circuit. In the figure, ■ is a horizontal oscillation circuit, 2 is a horizontal deflection yoke drive circuit, 3 is a horizontal deflection yoke, 4 is a left and right pincushion distortion correction transformer, 5 is a vertical oscillation circuit, and 6 is an input terminal to which a flybank pulse is input. .

7 is a balanced modulator, 8 is an adder, 9 is a vertical deflection yoke drive circuit, 10 is a vertical deflection yoke, 11 is a horizontal deflection yoke 3
12 is a deflection current flowing through the vertical deflection yoke 10 , 13 is an output oscillation waveform of the vertical oscillator 5 , and 14 is an output waveform of the balanced modulator 7 .

Regarding left and right pincushion distortion correction, the vertical pincushion distortion correction is carried out by modulating the current flowing through the deflection yoke 3 in a parabola shape with a vertical period as shown in waveform 11 by the transformer 4, thereby causing a large deflection at the center of the screen. , a horizontally periodic fly hack pulse is balanced-modulated with a sawtooth wave shown in waveform 13 to obtain a signal shown in waveform 14, which is superimposed on the sawtooth wave in adder 8, and the deflection current shown in waveform 12 is used for vertical deflection. Pour into yoke 9.

However, in such a conventional method, distortions as shown in FIG. 4 remain. In order to correct the distortion shown in FIG. 4(a), it is necessary to flow a correction current having a frequency twice the horizontal frequency. The distortion shown in FIG. 3B cannot be corrected completely due to the asymmetry of manufacturing variations in the cathode ray tube and the deflection yoke, and remains distortion.

As a means to solve the above-mentioned problem of residual distortion, the amount of distortion correction current corresponding to the vertical and horizontal scanning times is determined from the shape of raster distortion as shown in Figure 2, and stored in memory. There is a proposal to correct distortion by generating a correction current in accordance with the read value. A specific example of this is described in Japanese Patent Application Laid-Open No. 59-190780 entitled "Deflection Distortion Correction Circuit".

However, as described there, it is expected to be quite difficult to obtain a distortion correction current that takes into account variations in the deflection yoke from the rask distortion shape. Further, the drive voltage and drive current of the deflection yoke are much larger than the voltage and current within the video signal processing circuit, and it is expected that the distortion correction voltage and current will interfere with the video signal.

Furthermore, it is expected that there is a limit to the convergence accuracy when the three primary color signals of R, G, and B are deflected by the same deflection yoke. Furthermore, in order to improve convergence performance, it is necessary to improve large electrical components such as deflection yokes and cathode ray tubes, but these large electrical components are difficult to reduce in cost in the future, so I think that this direction is not desirable.

(Object of the Invention) An object of the present invention is to eliminate the problems of the prior art described above and to provide a distortion correction circuit for a cathode ray tube with less residual distortion.

[Summary of the invention]

As shown in Fig. 5, video signals are written in the video memory corresponding to the scanning lines in a barrel shape that corrects the raster distortion shown in Fig. 2, and when scanning with a cathode ray tube, the video memory is read out along the columns. Therefore, in the present invention, distortion correction is performed without flowing a distortion correction current to the deflection yoke.

In FIG. 5, 15 is a video memory whose number of bits is (M×N) where M is the number of scanning lines and N is the number of sampling points in one horizontal scanning period. Reference numeral 16 indicates an area in which video signal data is written on the video memory. You will notice that it has a barrel shape.

[Embodiments of the invention]

FIG. 1 shows a block diagram of an embodiment of the present invention.

In the figure, 17 is a memory that can be written and read at any time corresponding to one scanning line of one cathode ray tube, and 18 is a write address memory of the memory 17 determined from the rask shape. 19 is a video signal input terminal, 20 is a horizontal and vertical synchronization information detection circuit, and 21 is a cathode ray tube.

An overview of the operation will be explained.

The image memory 15 obtained from the rask shape is stored in the memory 18.
address is memorized. The video signal input from the input terminal 19 is supplied to the image memory 17 and also to the synchronization separation circuit 20, where vertical and horizontal synchronization signals are separated. Using this synchronization signal as a time reference, the write address of the image memory 17 is output from the write address memory 18, and the video signal is written to a desired address of the image memory.

The data has a barrel shape complementary to the rask distortion shape on the image memory, as shown in FIG. When reading, read in static column mode.

FIG. 6 shows an example of the data content in the image memory 17 during one horizontal scanning period at the beginning of the vertical scanning period, scanning lines on the shadow and polar bone canal surfaces, and an example of display content.

(A) is an example of a video signal of one horizontal period, a - y
indicates the sampling point. FIG. 1B shows the contents of the image memory 17 in FIG. 1, in which data of sampling points a to y are stored in a barrel shape on the memory.

The storage address depends on the contents stored in the write address memory 18 in advance.

For convenience of explanation, the horizontal direction of the memory is shown below.

The number of bits is 25 bits, which is several tenths of the actual number.

Figure (C) shows an example of data display when the contents of the image memory 17 are read out so that each column in the horizontal direction corresponds to a horizontal scanning line and displayed on a cathode ray tube, and the scanning lines are shown. be.

22 is an effective display screen frame of the display device, and 23-1 to 2
3-6 indicates a scanning line.

Raster ":"5'Cj as shown in Figure 6(C)
Even if the lb is not correct, the image content can be displayed without distortion. However, as can be inferred from the diagram in FIG. 6C, the number of effective scanning lines decreases on the left and right sides of the screen, and it is necessary to thin out the image data slightly. In the example of FIG. 6(C), there are 10 scanning lines at the left and right ends (top.

(5 pieces each at the lower end) decrease. As a result, the vertical resolution at both ends will be slightly degraded, but
In TV broadcasts received by a television receiver or the like, the importance of information around the screen is lower than that around the center, so it is thought that there is little practical problem.

FIG. 7 shows another embodiment of the present invention. The difference from FIG. 1 is that a scanning line number conversion circuit 24 is provided. The purpose of this is to increase the number of scanning lines by an amount corresponding to the amount of vertical pincushion distortion of the raster, thereby preventing the above-mentioned deterioration of vertical resolution at both left and right ends. The rate of increase in scanning lines is about 17% for a 110 degree deflection cathode tube, and for a 90 degree deflection, an even smaller rate is sufficient and the increase is not so large.

In this case, since the number of scanning lines increases in the center of the screen, it is necessary to interpolate the data.

Such data thinning and interpolation techniques have been thoroughly studied in the past and are well known to those skilled in the art.

As for left and right pincushion distortion, the thinning and interpolation operations described above are not necessary.

FIG. 8 shows yet another embodiment. The difference from FIG. 7 is that an A/D converter 25 and a D/A converter 26 are inserted. This serves as the image memory 17.
It assumes digital memory and is realistic.

Next, a specific example of a method for generating the contents of the write address memory 18 in FIG. 1 will be shown using FIGS. 9 and 10.

In FIG. 9, 27 is a television receiver to be adjusted; 28
1 is a coordinate reading device, 29 is a cable, 30 is an arithmetic device such as a microcomputer, 31 is a PROM writer, and 32 is a programmable ROM, which corresponds to the write address memory 17 in FIG.

Nine dots arranged horizontally and vertically as shown in FIG. 10 are displayed on the receiver 27, and the coordinates of their brightness are read by the coordinate reading device 28. If the coordinates of these nine points are known, the relationship between time and the scanning position of the cathode ray can be calculated using the vertical synchronization signal and the horizontal synchronization signal as time standards.

This is calculated by the calculation device 30, converted into write address data of the image memory 17, and written to the PROM writer 31.
Then, the address is written into the programmable ROM 32. The written PROM is installed in the television receiver 27, and distortion correction adjustment is completed.

In the figure, reference numerals 28, 29, 30, and 31 are adjustment equipment, which only need one cent on the production line. Note that the address generation method is not limited to this.

FIG. 11 shows still another embodiment of the present invention. This example:
This is a case where the present invention is applied independently to R, G, and B three primary color signals. 33 is an RGB separation matrix circuit; the image memory 17 is independently connected to three RGB signals (17-1);
(17-2) and (17-3). The write address memory 18 is also provided independently for the three RGB signals. The contents of the write address are shown in Figures 9 and 10.
This can be done by the method described above using the figures.

That is, the pattern shown in FIG. 10 is displayed on the cathode ray tube independently for R, G, and B, the coordinates are read, and the address is calculated by calculation. In addition, the D/A controller also has R, G, B
There are three for this purpose.

FIG. 12 shows yet another embodiment of the present invention. In the embodiments described above, it is assumed that the image memory 17 is a dual port type that can perform writing and reading at the same time, but in the case of FIG. This is done alternately. 34 and 35 are changeover switches, 36.3
7 corresponds to the image memory 17 in FIG.

〔Effect of the invention〕

According to the present invention, since deflection distortion can be corrected by rearranging image data on the image memory, deflection distortion can be suppressed to below the range of quantization error due to scanning lines. Furthermore, if the present invention is applied to the R, G, and B three primary colors independently, the convergence performance can be improved with the same accuracy.

From an economic perspective, not only does it eliminate the need for the pincushion distortion correction transformer used in the past, but it also makes it possible to reduce the manufacturing precision of large electrical components such as cathode ray tubes and deflection yokes, which reduces the cost of large components. Leads to. These large electrical components cannot be expected to be reduced in cost in the future, and their elimination and simplification will have a large effect.

Furthermore, conventionally, attachment of the deflection yoke to the cathode ray tube required precision and required manual labor, but this can now be done easily and cost reductions are desired.

On the other hand, what is increased by the present invention is the electrical circuit.

As is well known, these memories are small in size, and it is hoped that their costs will be significantly reduced in the future. Also,
The driving frequency of the electric circuit added according to the present invention is an integral multiple of the frequency of some reference signal of the image signal to be processed (for example, the color subcarrier in the case of a television receiver), and the frequency is 3 to 4 times the band. So there is almost no interference.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is an explanatory diagram showing an example of rask distortion in a cathode ray tube, FIG. 3 is a block diagram showing an example of a conventional deflection distortion correction circuit, and FIG. 4 is a block diagram showing an example of a conventional deflection distortion correction circuit. FIG. 5 is an explanatory diagram showing an example of residual deflection distortion after conventional correction. FIG. 5 is an explanatory diagram showing an example of the data area on the image memory according to the present invention. FIG. 6 is an explanatory diagram showing an example of the data area on the image memory according to the present invention and the cathode ray FIG. 7 is a block diagram showing another embodiment of the present invention, FIG. 8 is a diagram showing another embodiment of the present invention, and FIG. 9 is a diagram showing a display example of the present invention. FIG. 10 is an explanatory diagram showing a specific example of a method for generating the contents of the write address memory necessary for implementing the above, and FIG. 10 is an explanatory diagram showing an example of displaying dots.
FIG. 11 is a block diagram showing still another embodiment of the present invention,
FIG. 12 is a block diagram showing still another embodiment of the present invention,
It is. Explanation of symbols 17... Image memory, 18... Write address memory, 19... Video signal input terminal, 20... Horizontal and vertical synchronization information detection circuit, 21... Cathode ray management agent Patent attorney average Akio Ki No. 1 Fig. 2 Fig. 3 Fig. M 4 Fig. (d) (b) Fig. 5 N 6 Fig. 7 TA M 9

Claims (1)

[Claims] 1) An image memory into which a video signal is input, and a write address memory in which a write address of the image memory is determined and stored in advance so as to be able to correct deflection distortion, and The video signal written in the image memory according to the contents of the write address memory is sequentially read from the image memory as data and outputted to the display device, thereby making it possible to correct deflection distortion in the display device. Features a deflection distortion correction circuit.