JPS6285510A - Electronic circuit - Google Patents

Abstract

PURPOSE:To reduce the packing area of an IC on a substrate by controlling the input signal to be applied to each FF based on the clock signal so that plural FF undergo the transition of state with different edges of the clock signal. CONSTITUTION:The clock signal is supplied to a delay element 1 and the input terminal at one side of an exclusive OR gate 2. While the edge signal serving as the output of the element 1 is supplied to the input terminal at the other side of the element 1. Then the edge signal sent from the element 1 and signals D1 and Q1 are supplied to an AND/OR gate 3. While the edge signal sent from the element 1 and signals D2 and Q2 are supplied to an AND/OR gate 4 respectively. Thus the transition of state is given to an FF 5 only in a positive edge mode of the clock signal. While an FF 6 undergoes the transition of state only in a negative edge mode of the clock signal. As a result, the packing area of an IC is reduced on a substrate.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to electronic circuits.

[Prior Art] Conventionally, as shown in FIGS. 1(a) and 1(b), an electronic circuit is constructed of a plurality of flip-flops 20 that shift states ff, 3 at different edges of a clock (pulse). Are known.

[Problems to be solved by the invention] However, in the electronic circuit as described in -1-,
If flip-flops that change state at different edges of the clock are placed in the same IC package, the board
There was a drawback that the mounting area became large in L.

[Means for Solving the Problems] The present invention aims to eliminate the drawbacks of the conventional example described above. The L stage detects a pulse, generates a pulse, and commonly inputs the pulse to the clock terminal of a plurality of flip-flops. and means for controlling input signals to each flip-flop based on the input signal.

[Example] Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 2 shows an embodiment of the present invention, and has functions equivalent to those in FIG. 1. In FIG. 2, 1 is a delay element, and 2 is an exclusive OR (exclusive OR) for etch detection.
clusi ma e or) gate.

A clock (c1ock) signal is input to one input terminal of delay element l and gate 2. An edge signal as an output of the delay element 1 is input to the other input terminal of the gate 2. 3 and 4 are and-or
) gate, gate 3 receives the edge signal, D1 signal, and Q1 signal from delay element 1, and gate 4 receives the edge signal, D2 signal, and Q2 signal from delay element 1.
Input each signal.

5 and 6 are D (delay) type flip-flops, in which flip-flop 5 corresponds to the free flop whose state transitions at the positive edge in FIG. Corresponds to whelk. In this example, flip-flops 5 and 6 are both positive knee, de-shaped (i.e.,
common clock pins).

FIG. 3 shows a timing chart of each part in FIG.
d indicates the elongation time of the WK element 1.

The edge signal as the output of the delay element 1 is a signal obtained by extending the y, y clock signal by 8, and the exclusive OR output of this edge signal and the clock signal is supplied to the clock terminals of the two flip-flops 5 and 6. A control signal for this is obtained by an exclusive OR gate 2, which, as shown in FIG. 3, constitutes an edge detection circuit.

The control signal is set to 81 at the edge of the clock signal, and this control signal is applied to the clock terminals of the two flip-flops 5 and 6. The edge signal is low (
Low) and high during negative sex.
gh).

Flip-flop 5 operates as follows. That is,
The output signal of the AND-OR gate 3 is input to the D terminal of the flip-flop 5. This AND-OR gate 3 allows the flip-flop 5 to be connected to the positive signal of the clock signal.
It is possible to cause a transition to state 5 only at the time of an edge, and to prevent the state transition from occurring at the time of a negative φ etch.

That is, when the clock signal has a positive edge, the edge signal becomes low and the Dl signal is applied to the D terminal, and when the clock signal has a negative edge,
The edge signal becomes high, and the Q
l signal is added, and at this time the flip 20 knob 5 does not change state.

Flip-flop 6 operates as follows. That is,
The output signal of the AND-OR gate 4 is applied to the D terminal of the flip-flop 6. This gate 4 allows the Q2 signal to be input to the D terminal of the flip-flop 6 when the clock signal has a positive edge, and allows the D2 signal to be input to the D terminal of the flip-flop 6 when the clock signal has a negative edge. . Therefore, for this flip-flop 6, contrary to the flip-flop 5, the state does not shift when the clock signal is at the positive edge (from 1-1, the clock signal of 511i4 and the clock signal of FIG. .It can be seen that when 01 and 02 people are input in FIGS. 1 and 2, the Ql and 02 output signals are equivalent).

From the above 1-, since a plurality of flip-flops having a common clock terminal can be used, it is possible to obtain an electronic circuit with a small mounting area on the substrate l-. In particular, great effects can be obtained by using a package (eg, programmable array logic) that includes an AND-OR gate and a flip-flop.

FIG. 4 shows another embodiment of the invention, in which:
An electronic circuit using a J-type flip-flop is shown.

In FIG. 4, the clock signals, edge signals and control signals are exactly the same timing as in FIG. 3.

++ is′? ! The extension element 12 is an exclusive OR gate, and inputs a clock signal to one input terminal of the hu element II and the gate 12. The edge signal from the d-bread element 11 is input to the other input terminal of the gate 12 .

+3A, 13B, 14A, and 14B are AND gates, and each output signal is input to the terminals of J of flip-flops 15 and 18, respectively. Also, each game) 14A, 13B
and a delay element 11 at one input terminal of 14A and 14B.
The etching signal from Jl is inputted in inverted and non-inverted format, and the other input terminal is Jl and 1. J2. Input two signals to each.

Therefore, for flip-flop 15, when the edge signals to the two AND gates are high, both terminals of J are low (Lo), and at the negative edge of the clock signal, the state is It does not change.

Similarly, regarding the flip-flop 16, the clock signal -
The state does not change with the positive knee and ji.

[Effects of the Invention] As explained above, according to the present invention, it is possible to use flip-flops that share a common clock terminal, and for example, the number of packages can be reduced by reducing the mounting surface area of the IC. can.

[Brief explanation of drawings]

Figures 1 (a) and (b) are diagrams showing an electronic circuit, Figure 2 is a diagram showing an embodiment of the present invention, Figure 3 is a timing chart of each part of Figure 2, and Figure 4 is a diagram showing the present invention. It is a figure which shows another Example of. l...Delay element. 2...Exclusive or gate, 3.4...
And or gate, 5.6...D type flip-flop. Figure 2 Figure 3

Claims (1)

[Scope of Claims] A plurality of flip-flops having a common clock terminal; and means for detecting an edge of a clock signal to generate a pulse, and inputting the pulse in common to the clock terminal of the plurality of flip-flops. and means for controlling an input signal to each of the flip-flops based on a clock signal so that the state of each of the plurality of flip-flops is changed at different edges of the clock signal.