JPS628027B2 - - Google Patents
Info
- Publication number
- JPS628027B2 JPS628027B2 JP15614080A JP15614080A JPS628027B2 JP S628027 B2 JPS628027 B2 JP S628027B2 JP 15614080 A JP15614080 A JP 15614080A JP 15614080 A JP15614080 A JP 15614080A JP S628027 B2 JPS628027 B2 JP S628027B2
- Authority
- JP
- Japan
- Prior art keywords
- oxidation
- oxide film
- substrate
- material layer
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000000758 substrate Substances 0.000 claims description 39
- 230000003647 oxidation Effects 0.000 claims description 38
- 238000007254 oxidation reaction Methods 0.000 claims description 38
- 239000000463 material Substances 0.000 claims description 37
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 29
- 239000004065 semiconductor Substances 0.000 claims description 21
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 19
- 238000002955 isolation Methods 0.000 claims description 19
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 19
- 238000004519 manufacturing process Methods 0.000 claims description 15
- 238000000034 method Methods 0.000 claims description 15
- 238000005530 etching Methods 0.000 claims description 8
- 239000012535 impurity Substances 0.000 claims description 6
- 230000001590 oxidative effect Effects 0.000 claims description 5
- YXTPWUNVHCYOSP-UHFFFAOYSA-N bis($l^{2}-silanylidene)molybdenum Chemical compound [Si]=[Mo]=[Si] YXTPWUNVHCYOSP-UHFFFAOYSA-N 0.000 claims description 2
- 229910021344 molybdenum silicide Inorganic materials 0.000 claims description 2
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims description 2
- 229910021342 tungsten silicide Inorganic materials 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 5
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 229910052796 boron Inorganic materials 0.000 description 4
- 230000007547 defect Effects 0.000 description 4
- 238000000992 sputter etching Methods 0.000 description 4
- 241000293849 Cordylanthus Species 0.000 description 3
- -1 boron ions Chemical class 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- 210000003323 beak Anatomy 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000008030 elimination Effects 0.000 description 1
- 238000003379 elimination reaction Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- RLOWWWKZYUNIDI-UHFFFAOYSA-N phosphinic chloride Chemical compound ClP=O RLOWWWKZYUNIDI-UHFFFAOYSA-N 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Local Oxidation Of Silicon (AREA)
- Drying Of Semiconductors (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置の製造方法に関し、特に絶
縁物による素子分離技術を改良した半導体装置の
製造方法に係る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device that improves element isolation technology using an insulator.
半導体集積回路における分離技術に関しては高
集積化、製造プロセスの容易化を図るものとして
一般に分離領域を選択酸化技術によつて形成した
酸化膜を使用するものが知られている。この方式
によれば、能動領域の周囲が酸化膜によつて取り
囲まれているため、ベース拡散等においてセルフ
アラインメントが可能で従来のようなマスク含せ
のための不要な部分が省略でき、高集積化が可能
となり、また側面が深い酸化膜により構成された
ことによつて接合容量は桁違いに減少する。しか
しながら、この方式ではシリコン基板中に熱酸化
膜を選択的に埋没させる構造のため、シリコン基
板に大きな歪が生じ、素子の電気的特性を劣化さ
せ、耐酸化性マスクの構造、構成、膜厚及び選択
酸化条件、時にはシリコン基板そのものの材料自
身の選択に著しい制限を与えている。これは、例
えば文献IEDM“High Pressure Oxidation for
Isolation of High Speed Bipolar Devices”
1979年PP340〜343に記載されている。 Regarding isolation technology in semiconductor integrated circuits, it is generally known to use an oxide film formed by selective oxidation technology as an isolation region in order to achieve high integration and ease of manufacturing process. According to this method, since the active region is surrounded by an oxide film, self-alignment is possible in base diffusion, etc., unnecessary parts for mask inclusion can be omitted, and high integration is possible. The junction capacitance is reduced by an order of magnitude because the side surfaces are made of a deep oxide film. However, since this method has a structure in which a thermal oxide film is selectively buried in the silicon substrate, large distortions occur in the silicon substrate, deteriorating the electrical characteristics of the device, and reducing the structure, composition, and film thickness of the oxidation-resistant mask. Also, selective oxidation conditions, and sometimes the selection of the material of the silicon substrate itself, are severely restricted. This can be seen, for example, in the literature IEDM “High Pressure Oxidation for
Isolation of High Speed Bipolar Devices”
Described in 1979 PP340-343.
また、窒化シリコン膜をマスクとして熱酸化を
行なうと、“ホワイトリボン”と称するシリコン
ナイトライド膜が窒化シリコン膜の下のSi基板中
に形成され、これが素子の耐圧不良の原因とな
る。更に、耐酸化性マスクとして窒化シリコン膜
と酸化膜からなる２重層のものを使用するため、
１μｍに近いバーズビークが窒化シリコン膜下に
喰い込み、その結果２μｍ以下の素子間分離膜の
形成が困難であつた。これは、例えば文献Birds
Beak、Configuration and Elimination of Gate
Oxide Thinnig Produced during Selection
Oxidation”1980年 P216〜222 Ｊ、Ｅ、Ｃ、Ｓ
に記載されている。 Furthermore, when thermal oxidation is performed using a silicon nitride film as a mask, a silicon nitride film called a "white ribbon" is formed in the Si substrate under the silicon nitride film, which causes a breakdown voltage failure of the device. Furthermore, since a double layer consisting of a silicon nitride film and an oxide film is used as an oxidation-resistant mask,
The bird's beak, which is close to 1 .mu.m, digs into the bottom of the silicon nitride film, and as a result, it is difficult to form an element isolation film of 2 .mu.m or less. This is for example the literature Birds
Beak, Configuration and Elimination of Gate
Oxide Thinnig Produced during Selection
Oxidation”1980 P216-222 J, E, C, S
It is described in.
本発明は上記欠点を解消するためになされたも
ので、半導体基板上に該基板より酸化速度の速い
材料層を形成し、この材料層上に直接窒化シリコ
ンからなる耐酸化性マスクを選択的に形成した
後、該マスクを用いて材料層を選択酸化し、ひき
つづき、マスク除去、その下の残存材料層の少な
くとも一部除去を行なうことによつて、選択酸化
時、半導体基板への熱影響による欠陥発生を防止
し、かつ同選択酸化時のベーズビークの発生を抑
制すると共に材料層上へのオキシナイトライド膜
の生成を防止でき、ひいては電気特性が良好で、
変換差の小さい微細素子に適した半導体装置の製
造方法を提供しようとするものである。 The present invention has been made to eliminate the above-mentioned drawbacks, and involves forming a layer of a material with a faster oxidation rate than the substrate on a semiconductor substrate, and selectively applying an oxidation-resistant mask made of silicon nitride directly on this material layer. After the formation, the material layer is selectively oxidized using the mask, and then the mask is removed and at least a portion of the remaining material layer underneath is removed. It can prevent the occurrence of defects, suppress the generation of Baise's beak during selective oxidation, and prevent the formation of an oxynitride film on the material layer, resulting in good electrical properties.
The present invention aims to provide a method for manufacturing a semiconductor device suitable for fine elements with small conversion differences.
すなわち、本発明は半導体基板上に該基板より
酸化速度の速い材料層を形成する工程と、この材
料層上に直接窒化シリコンからなる耐酸化性マス
クを選択的に形成した後、該マスクを用いて前記
材料層を選択酸化し、厚い酸化膜を形成する工程
と、前記耐酸化性マスクを除去した後、露出した
残存材料層の少なくとも一部を除去する工程とを
具備したことを特徴とするものである。 That is, the present invention involves the steps of forming a layer of a material with a faster oxidation rate than the substrate on a semiconductor substrate, selectively forming an oxidation-resistant mask made of silicon nitride directly on this material layer, and then using the mask. The method is characterized by comprising a step of selectively oxidizing the material layer to form a thick oxide film, and a step of removing at least a part of the exposed remaining material layer after removing the oxidation-resistant mask. It is something.
本発明における半導体基板より酸化速度の速い
材料層は選択酸化により素子間分離膜としての酸
化膜を形成するために利用される。かかる材料と
しては、例えばリン、砒素、ボロンなどの不純物
が高濃度ドープされた多結晶シリコン、或いはモ
リブデンシリサイド、タングステンシリサイド、
タンタルシリサイドなどの金属硅化物等を挙げる
ことができる。なお、材料層を半導体基板上に形
成するにあたつては、酸化膜を介して材料層を形
成してもよい。このように基板と材料層の間に酸
化膜を介在させることにより、特に材料層として
高濃度不純物ドープ多結晶シリコン層を用いた場
合、選択酸化時に該多結晶シリコン層中の不純物
が基板中に拡散するのを該酸化膜により阻止でき
る利点を有する。また、材料層として不純物ドー
プ多結晶シリコン層を用い、この残存多結晶シリ
コン層をエツチングするに際しても、前記酸化膜
が基板に対するエツチングストツパとして作用す
る。 In the present invention, the material layer having a faster oxidation rate than the semiconductor substrate is used to form an oxide film as an isolation film between elements by selective oxidation. Examples of such materials include polycrystalline silicon heavily doped with impurities such as phosphorus, arsenic, and boron, molybdenum silicide, tungsten silicide,
Examples include metal silicides such as tantalum silicide. Note that when forming the material layer on the semiconductor substrate, the material layer may be formed via an oxide film. By interposing the oxide film between the substrate and the material layer in this way, especially when a highly impurity-doped polycrystalline silicon layer is used as the material layer, impurities in the polycrystalline silicon layer can be absorbed into the substrate during selective oxidation. This oxide film has the advantage of preventing diffusion. Furthermore, when an impurity-doped polycrystalline silicon layer is used as the material layer and the remaining polycrystalline silicon layer is etched, the oxide film acts as an etching stopper for the substrate.
本発明においては窒化シリコンからなる耐酸化
性マスクを材料層上に直接形成することを特長と
し、かかる状態において選択酸化を行なうことに
よつて、耐酸化性マスク下に酸化膜が喰い込む、
いわゆるバーズビークを著しく抑制できると共
に、マスク下の材料層表面の一部にオキシナイト
ライド膜が生成されるのを防止できる。なお、オ
キシナイトライド膜が生成されないことによる効
果は以下の如くである。即ち、選択酸化により材
料層の露出部付近に厚い酸化膜を形成し、マスク
を除去した後、残存材料層を除去するが、この除
去にあたつては形成すべき素子間分離膜がオーバ
ーハング構造となるのを避けるために反応性スパ
ツタイオンエツチングにより除去する。しかし、
このエツチング時に残存した帯状のオキシナイト
ライド膜がエツチングマスクとして作用し、厚い
酸化膜に沿つて材料層が残る。こうした状態で残
つた材料層を熱酸化して酸化膜に変換すると、素
子間分離膜の面積が広くなる、つまり寸法変換差
が大きくなり、素子の微細化の妨げとなる。した
がつて、選択酸化時に、耐酸化性マスク下の材料
層表面の一部にオキシナイトライド膜が生じない
ことは、素子の微細化の点から極めて有益であ
る。 The present invention is characterized in that an oxidation-resistant mask made of silicon nitride is formed directly on the material layer, and by performing selective oxidation in such a state, the oxide film digs under the oxidation-resistant mask.
So-called bird's beak can be significantly suppressed, and the formation of an oxynitride film on a part of the surface of the material layer under the mask can be prevented. The effects of not producing an oxynitride film are as follows. That is, a thick oxide film is formed near the exposed part of the material layer by selective oxidation, and after the mask is removed, the remaining material layer is removed, but during this removal, the isolation film to be formed is not overhanged. It is removed by reactive sputter ion etching to avoid structures. but,
The band-shaped oxynitride film remaining during this etching acts as an etching mask, and a material layer remains along the thick oxide film. If the material layer remaining in such a state is thermally oxidized and converted into an oxide film, the area of the isolation film between elements will increase, that is, the difference in dimensional conversion will increase, which will hinder the miniaturization of elements. Therefore, it is extremely beneficial from the viewpoint of device miniaturization that an oxynitride film is not formed on a part of the surface of the material layer under the oxidation-resistant mask during selective oxidation.
本発明における残存材料層の除去手段として
は、酸化膜端部下がオーバーハング構造となるの
を避けるために、基板に対して略垂直に残存材料
層をエツチングし得る反応性スパツタイオンエツ
チング法、イオンビームエツチング法などの異方
性エツチング法を採用することが望ましい。 The means for removing the remaining material layer in the present invention includes a reactive sputter ion etching method that can etch the remaining material layer approximately perpendicularly to the substrate in order to avoid an overhang structure under the edge of the oxide film; It is desirable to employ an anisotropic etching method such as ion beam etching.
次に、本発明をｎチヤンネルMOSICの製造に
適用した例について第１図〜第６図を参照して説
明する。 Next, an example in which the present invention is applied to the manufacture of an n-channel MOSIC will be described with reference to FIGS. 1 to 6.
実施例
〔〕 まず、ｐ型の単結晶シリコン基板１を熱
酸化処理して、その主面に厚さ1000A゜の熱酸
化膜２を成長させた後、熱酸化膜２上に多結晶
シリコンをPOCl3雰囲気中で気相成長させ、基
板より酸化速度の速い材料層である厚さ4000A
゜のリンドープ多結晶シリコン層３を堆積した
（第１図図示）。つづいて、多結晶シリコン層３
上に直接厚さ2000A゜の窒化シリコン膜を気相
成長法により堆積し、反応性スパツタイオンエ
ツチングを用いてフオトエツチングプロセスに
よりパターニングして幅（Ｗ）が２μｍ、パタ
ーンピツチ（Ｐ）が２μｍの複数の窒化シリコ
ンパターン４……を形成した。ひきつづき、窒
化シリコンパターン４……をマスクとしてボロ
ンを出力180KeV、ドーズ量４×1013／cm2の条
件でイオン注入し、活性化して基板１にp+型
のチヤンネルストツパ５……を形成した（第２
図図示）。なお、この場合窒化シリコンパター
ンの形成に使用したフオトレジストパターンを
マスクとしてボロンのイオン注入を行なつても
よい。Example [1] First, a p-type single-crystal silicon substrate 1 is thermally oxidized to grow a thermal oxide film 2 with a thickness of 1000 A° on its main surface, and then polycrystalline silicon is deposited on the thermal oxide film 2. 4000A thick, which is a layer of material that oxidizes faster than the substrate, grown in a vapor phase in a POCl 3 atmosphere.
A phosphorus-doped polycrystalline silicon layer 3 of .degree. was deposited (as shown in FIG. 1). Next, polycrystalline silicon layer 3
A silicon nitride film with a thickness of 2000 A° was deposited directly on top by vapor phase epitaxy, and patterned by a photo-etching process using reactive sputter ion etching to obtain a film with a width (W) of 2 μm and a pattern pitch (P) of 2 μm. A plurality of silicon nitride patterns 4... were formed. Subsequently, using the silicon nitride pattern 4 as a mask, boron ions are implanted at an output of 180 KeV and a dose of 4×10 13 /cm 2 and activated to form a p + type channel stopper 5 on the substrate 1. I did it (second
(Illustrated) In this case, boron ions may be implanted using the photoresist pattern used to form the silicon nitride pattern as a mask.
〔〕 次いで、窒化シリコンパターン４……を
耐酸化性マスクとして多結晶シリコン層３を選
択酸化した。この時、多結晶シリコン層３の露
出部付近が酸化されて寸法変換差が0.15μｍの
素子間分離用の厚さ6000A゜の厚い酸化膜６が
形成された（第３図図示）。また、窒化シリコ
ンパターン４……下の厚い酸化膜６に沿う残存
多結晶シリコン層３′の表面部分にはオキシナ
イトライド膜は全く生じなかつた。更に、同選
択酸化において、多結晶シリコン層３′中のリ
ンがシリコン基板１に拡散するのを熱酸化膜２
により阻止された。[] Next, the polycrystalline silicon layer 3 was selectively oxidized using the silicon nitride pattern 4 as an oxidation-resistant mask. At this time, the vicinity of the exposed portion of the polycrystalline silicon layer 3 was oxidized to form a thick oxide film 6 with a thickness of 6000 A° for device isolation with a dimensional conversion difference of 0.15 μm (as shown in FIG. 3). Moreover, no oxynitride film was formed on the surface portion of the remaining polycrystalline silicon layer 3' along the thick oxide film 6 below the silicon nitride pattern 4. Furthermore, in the same selective oxidation, the thermal oxide film 2 prevents phosphorus in the polycrystalline silicon layer 3' from diffusing into the silicon substrate 1.
was prevented by.
〔〕 次いで、窒化シリコンパターン４……を
CF4系のドライエツチングにより除去した後、
残存多結晶シリコン層３′をCCl4系の反応性ス
パツタイオンエツチングで除去した。この時、
残存多結晶シリコン層３′表面にはオキシナイ
トライド膜が存在していないため、厚い酸化膜
６に対してセルフアラインで該多結晶シリコン
層３′が略垂直にエツチングされ、第４図に示
す如く厚い酸化膜６のオーバーハング部に多結
晶シリコン層３″が残つた。つづいて、露出し
た熱酸化膜２部分をフツ化アンモニウム液で除
去して基板１表面の一部を露出させた後、熱酸
化処理を施した。この時、単結晶シリコン基板
１の露出面に厚さ400A゜のゲート酸化膜７が
成長されると同時に、オーバーハング部に残つ
た多結晶シリコン層３″が酸化膜となり前記厚
い酸化膜と共にオーバーハングのない素子間分
離膜８が形成された（第５図図示）。ひきつづ
き素子間分離膜８をマスクとしてボロンを出力
40KeV、ドーズ量３×1011／cm2の条件でゲート
酸化膜７下の基板１のチヤンネル部にイオン注
入して閾値制御のためのp+型不純物領域９を
形成した（同第５図図示）。[] Next, silicon nitride pattern 4...
After removing by CF 4 dry etching,
The remaining polycrystalline silicon layer 3' was removed by CCl 4 -based reactive sputter ion etching. At this time,
Since there is no oxynitride film on the surface of the remaining polycrystalline silicon layer 3', the polycrystalline silicon layer 3' is self-aligned and etched substantially perpendicularly to the thick oxide film 6, as shown in FIG. A polycrystalline silicon layer 3'' remained on the overhang portion of the thick oxide film 6.Next, the exposed thermal oxide film 2 was removed with an ammonium fluoride solution to expose a part of the surface of the substrate 1. , thermal oxidation treatment was performed.At this time, a gate oxide film 7 with a thickness of 400A° was grown on the exposed surface of the single crystal silicon substrate 1, and at the same time, the polycrystalline silicon layer 3'' remaining in the overhang portion was oxidized. An interelement isolation film 8 without overhang was formed together with the thick oxide film (as shown in FIG. 5). Continue to output boron using the interelement isolation film 8 as a mask
Ions were implanted into the channel part of the substrate 1 under the gate oxide film 7 under conditions of 40 KeV and a dose of 3×10 11 /cm 2 to form a p + type impurity region 9 for threshold control (as shown in FIG. 5). ).
〔〕 次いで、常法にしたがつてゲート酸化膜
７上に多結晶シリコンからなるゲート電極１０
を形成し、同ゲート電極１０をマスクとして砒
素のイオン注入、活性化を施してn+型のソー
ス、ドレイン（図示せず）を形成し、CVD−
SiO2膜、Al酸線形成等を経た後、1000℃、60
分間の熱処理を施して閾値が約0.8Vのｎチヤ
ンネルMOSICを製造した（第６図図示）。[] Next, a gate electrode 10 made of polycrystalline silicon is formed on the gate oxide film 7 according to a conventional method.
is formed, and using the same gate electrode 10 as a mask, arsenic ions are implanted and activated to form n + type sources and drains (not shown), and CVD-
After SiO 2 film, Al acid ray formation, etc., 1000℃, 60
An n-channel MOSIC with a threshold value of about 0.8V was manufactured by performing heat treatment for 1 minute (as shown in FIG. 6).
しかして、本発明は単結晶シリコン基板１上
に設けられた該基板より酸化速度の速いリンド
ープ多結晶シリコン層３を選択酸化することに
より素子間分離膜を形成するため、基板１への
熱影響を抑制でき、熱影響に伴なう基板１への
欠陥発生、不純物の再拡散を少なくできる。ま
た、従来の選択酸化法の如く基板１を直接酸化
して素子間分離膜を造るのではなく、基板１上
のリンドープ多結晶シリコン層３の選択酸化に
より素子間分離膜８を形成するため、基板１へ
の多大なストレス発生を防止できる。しかも、
多結晶シリコン層３上に直接窒化シリコンパタ
ーン４……を形成した選択酸化においてはオキ
シナイトライド膜が多結晶シリコン層３上の一
部に形成されないことは勿論、基板１上にも全
く形成されない。したがつて欠陥の極めて少な
い単結晶シリコン基板１を有することから、電
気特性が良好で高信頼性のｎチヤンネル
MOSICを製造できる。 Therefore, in the present invention, since the device isolation film is formed by selectively oxidizing the phosphorus-doped polycrystalline silicon layer 3 provided on the single-crystal silicon substrate 1, which has a faster oxidation rate than the substrate, the thermal influence on the substrate 1 is reduced. It is possible to suppress the occurrence of defects in the substrate 1 and the re-diffusion of impurities due to thermal effects. In addition, since the element isolation film 8 is not formed by directly oxidizing the substrate 1 as in the conventional selective oxidation method, but the element isolation film 8 is formed by selective oxidation of the phosphorus-doped polycrystalline silicon layer 3 on the substrate 1. It is possible to prevent the occurrence of a large amount of stress on the substrate 1. Moreover,
In selective oxidation in which a silicon nitride pattern 4 is directly formed on the polycrystalline silicon layer 3, an oxynitride film is not formed on a part of the polycrystalline silicon layer 3, and is not formed on the substrate 1 at all. . Therefore, since it has a single crystal silicon substrate 1 with extremely few defects, it can be used as an N-channel with good electrical characteristics and high reliability.
Can manufacture MOSIC.
また、リンドープ多結晶シリコン層３の選択
酸化時、窒化シリコンパターン４……下の多結
晶シリコン層３部分への酸化膜の喰い込み、つ
まリバーズビークは0.15μｍに抑えられるこ
と、並びに残存多結晶シリコン層３′表面の一
部にオキシナイトライド膜が生成せず、厚い酸
化膜６に対してセルフアラインで該多結晶シリ
コン層３′を略垂直にエツチングできることに
より、寸法交換差が少なく微細な素子分離膜８
を形成でき、その結果素子の微細化が達成され
たMOSICを得ることができる。 In addition, during selective oxidation of the phosphorus-doped polycrystalline silicon layer 3, it is noted that the oxidation film digging into the polycrystalline silicon layer 3 below the silicon nitride pattern 4 and the reverse beak are suppressed to 0.15 μm, and that the remaining polycrystalline silicon layer 3 is suppressed to 0.15 μm. No oxynitride film is formed on a part of the surface of the silicon layer 3', and the polycrystalline silicon layer 3' can be etched almost perpendicularly in self-alignment with respect to the thick oxide film 6, so that the difference in dimensional exchange is small and fine etching is possible. Element isolation film 8
As a result, a MOSIC with miniaturized elements can be obtained.
なお、本発明は上記実施例の如きｎチヤンネ
ルMOSICの製造のみに限らず、ｐチヤンネル
MOSIC、バイポーラIC、I2L、CCD等にも同様
に適用することができる。 Note that the present invention is not limited to the manufacture of n-channel MOSICs as in the above embodiments, but also applies to p-channel MOSICs.
It can be similarly applied to MOSIC, bipolar IC, I 2 L, CCD, etc.
以上詳述した如く、本発明によれば半導体基板
上の材料層を選択酸化することにより基板への欠
陥発生を少なくして素子間分離膜を形成でき、し
かも、選択酸化時のマスク下へのバードビークの
発生を抑制できると共に残存材料層の除去時にエ
ツチングマスクとして働らくオキシナイトライド
膜の生成がなく微細な素子間分離膜の形成が可能
となり、もつて、電気的特性が良好で素子の微細
化を達成した半導体装置の製造方法を提供できる
ものである。 As detailed above, according to the present invention, by selectively oxidizing a material layer on a semiconductor substrate, it is possible to form an isolation film between elements while reducing the occurrence of defects on the substrate. In addition to suppressing the occurrence of bird's beak, it also eliminates the formation of an oxynitride film that acts as an etching mask when removing the remaining material layer, making it possible to form a fine isolation film between devices. Accordingly, it is possible to provide a method for manufacturing a semiconductor device that achieves the following.
第１図〜第６図は本発明の実施例におけるｎチ
ヤンネルMOSICの製造工程を示す断面図であ
る。
１……ｐ型単結晶シリコン基板、２……熱酸化
膜、３……リンドープ多結晶シリコン層、３′…
…残存多結晶シリコン層、４……窒化シリコンパ
ターン、５……p+型のチヤンネルストツパ、６
……厚い酸化膜、７……ゲート酸化膜、８……素
子間分離膜、９……p+型不純物領域、１０……
ゲート電極。
1 to 6 are cross-sectional views showing the manufacturing process of an n-channel MOSIC according to an embodiment of the present invention. 1...p-type single crystal silicon substrate, 2...thermal oxide film, 3...phosphorus-doped polycrystalline silicon layer, 3'...
...Residual polycrystalline silicon layer, 4...Silicon nitride pattern, 5...P + type channel stopper, 6
... Thick oxide film, 7 ... Gate oxide film, 8 ... Interelement isolation film, 9 ... P + type impurity region, 10 ...
gate electrode.
Claims (1)
料層を形成する工程と、この材料層上に直接窒化
シリコンからなる耐酸化性マスクを選択的に形成
した後、該マスクを用いて前記材料層を選択酸化
し、厚い酸化膜を形成する工程と、前記耐酸化性
マスクを除去した後、露出した残存材料層の少な
くとも一部を除去する工程とを具備したことを特
徴とする半導体装置の製造方法。 ２ 半導体基板上に該基板より酸化速度の速い材
料層を酸化膜を介して形成することを特徴とする
特許請求の範囲第１項記載の半導体装置の製造方
法。 ３ 半導体基板より酸化速度の速い材料として、
高濃度不純物ドープ多結晶シリコン、モリブデン
シリサイド及びタングステンシリサイドのうちの
少なくとも１つの材料を用いることを特徴とする
特許請求の範囲第１項又は第２項記載の半導体装
置の製造方法。 ４ 耐酸化性マスクを半導体基板と同導電型の不
純物のドーピングマスクとして用いることを特徴
とする特許請求の範囲第１項ないし第３項いずれ
か記載の半導体装置の製造方法。 ５ 露出した残存材料層の少なくとも一部を除去
するに際し、異方性エツチングを用いて行なうこ
とを特徴とする特許請求の範囲第１項ないし第４
項いずれか記載の半導体装置の製造方法。 ６ 選択酸化により形成された酸化膜が素子間分
離膜であることを特徴とする特許請求の範囲第１
項ないし第５項いずれか記載の半導体装置の製造
方法。[Claims] 1. A step of forming a layer of a material having a higher oxidation rate than that of the substrate on a semiconductor substrate, and selectively forming an oxidation-resistant mask made of silicon nitride directly on this material layer, and then forming the mask. The method is characterized by comprising the steps of selectively oxidizing the material layer using a method to form a thick oxide film, and removing at least a portion of the exposed remaining material layer after removing the oxidation-resistant mask. A method for manufacturing a semiconductor device. 2. A method of manufacturing a semiconductor device according to claim 1, characterized in that a layer of material whose oxidation rate is faster than that of the semiconductor substrate is formed on the semiconductor substrate via an oxide film. 3 As a material with a faster oxidation rate than a semiconductor substrate,
3. The method of manufacturing a semiconductor device according to claim 1, wherein at least one material selected from highly impurity-doped polycrystalline silicon, molybdenum silicide, and tungsten silicide is used. 4. A method for manufacturing a semiconductor device according to any one of claims 1 to 3, characterized in that an oxidation-resistant mask is used as a doping mask for impurities of the same conductivity type as the semiconductor substrate. 5. Claims 1 to 4, characterized in that anisotropic etching is used to remove at least a portion of the exposed remaining material layer.
A method for manufacturing a semiconductor device according to any one of paragraphs. 6 Claim 1, characterized in that the oxide film formed by selective oxidation is an isolation film between elements.
6. A method for manufacturing a semiconductor device according to any one of items 5 to 5.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15614080A JPS5779638A (en) | 1980-11-06 | 1980-11-06 | Manufacture of semiconductor device |
| DE8181305215T DE3168688D1 (en) | 1980-11-06 | 1981-11-02 | Method for manufacturing a semiconductor device |
| EP81305215A EP0051488B1 (en) | 1980-11-06 | 1981-11-02 | Method for manufacturing a semiconductor device |
| US06/317,616 US4459325A (en) | 1980-11-06 | 1981-11-03 | Semiconductor device and method for manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15614080A JPS5779638A (en) | 1980-11-06 | 1980-11-06 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5779638A JPS5779638A (en) | 1982-05-18 |
| JPS628027B2 true JPS628027B2 (en) | 1987-02-20 |
Family
ID=15621193
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15614080A Granted JPS5779638A (en) | 1980-11-06 | 1980-11-06 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5779638A (en) |
-
1980
- 1980-11-06 JP JP15614080A patent/JPS5779638A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5779638A (en) | 1982-05-18 |
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