JPS6278859A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPS6278859A JPS6278859A JP60217873A JP21787385A JPS6278859A JP S6278859 A JPS6278859 A JP S6278859A JP 60217873 A JP60217873 A JP 60217873A JP 21787385 A JP21787385 A JP 21787385A JP S6278859 A JPS6278859 A JP S6278859A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- semiconductor integrated
- cooling
- substrate
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48464—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は、高密度混成集積回路において大規模集積回路
チップから効率の良い熱放散をおこなうために冷却構造
を備えた半導体集積回路装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a semiconductor integrated circuit device having a cooling structure for efficient heat dissipation from a large-scale integrated circuit chip in a high-density hybrid integrated circuit.
近年、半導体技術の急速な進歩にともなって、超ＬＳＩ
が作られ使用されている。この超ＬＳＩワット以上の大
きな電力を消費している。このため、この種の半導体集
積回路装置は、チクプ当）の発熱量が増大し、冷却が難
しくかつ熱設計が難しくなっている。In recent years, with the rapid progress of semiconductor technology, ultra-LSI
is made and used. It consumes more power than this super LSI watt. For this reason, in this type of semiconductor integrated circuit device, the amount of heat generated by the chips increases, making cooling and thermal design difficult.
以下、従来技術による半導体集積回路装置の構造とその
放熱方法を図面を用いて説明する。The structure of a conventional semiconductor integrated circuit device and its heat dissipation method will be described below with reference to the drawings.
第５図は従来技術の半導体集積回路装置の断面図、第６
図は従来技術の冷却用金属棒を有する半導体集積回路装
置の断面図、第７図は従来技術のセラミックパッケージ
を施した半導体集積回路装置の断面図である。第５図力
）ら第７図において、１は半導体集積回路チップ、２は
セラミック基板。FIG. 5 is a cross-sectional view of a conventional semiconductor integrated circuit device, and FIG.
The figure is a sectional view of a semiconductor integrated circuit device having a conventional cooling metal rod, and FIG. 7 is a sectional view of a semiconductor integrated circuit device provided with a conventional ceramic package. In Figure 5) and Figure 7, 1 is a semiconductor integrated circuit chip, and 2 is a ceramic substrate.
３はハンダ、４は金属棒、５はリード端子、６ＦｉＡｕ
−！９１共晶体、７はＡｇろう、８はガラス、９は放熱
フィン、１０はワイヤである。3 is solder, 4 is metal rod, 5 is lead terminal, 6FiAu
-! 91 is a eutectic, 7 is Ag solder, 8 is glass, 9 is a radiation fin, and 10 is a wire.
第５図に示す半導体集積回路装置は５多数の半導体集積
回路チップ１がハンダ３等により１回路基板であるセラ
ミック基板２にフェイスダウン実装されているため、放
熱が悪い。一般にこの種の放熱は、半導体集積回路チッ
プ１の裏面（填５図の半導体チップ１の上部）から、該
半導体集積回路チップ１０発熱量の程度にしたがって、
空気の自然対流、空気の強制対流によっておこなわれて
いる。さらに発熱量の多い場合には、７レオン液体の強
制対流、７レオン液体の沸騰冷却、水の強制対流、水の
沸騰冷却、金属片による冷却等の冷却方法が考えられて
いるが、冷却のシステムが非常に複雑である欠点を有し
ている。The semiconductor integrated circuit device shown in FIG. 5 has poor heat dissipation because five semiconductor integrated circuit chips 1 are mounted face down on a ceramic substrate 2, which is one circuit board, with solder 3 or the like. Generally, this type of heat radiation is performed from the back surface of the semiconductor integrated circuit chip 1 (the upper part of the semiconductor chip 1 in Figure 5), depending on the amount of heat generated by the semiconductor integrated circuit chip 10.
This is done by natural convection of air and forced convection of air. In cases where the amount of heat generated is even larger, cooling methods such as forced convection of 7 Leon liquid, boiling cooling of 7 Leon liquid, forced convection of water, boiling cooling of water, and cooling with metal pieces have been considered. The system has the disadvantage of being very complex.
第６図は、金属片による冷却の例である。この方法はチ
ップ１の裏面に冷却された金属棒を押当てて冷却をおこ
なうため、かなシの放熱が得られる。しかし、全体のモ
ジュールにおいては、多数の金属棒とこれらを冷却する
システムが必要で。FIG. 6 is an example of cooling using a metal piece. In this method, a cooled metal rod is pressed against the back surface of the chip 1 for cooling, so that a large degree of heat radiation can be obtained. However, the entire module requires a large number of metal rods and a system to cool them.
複雑な冷却システムとなる欠点を有している。It has the disadvantage of requiring a complex cooling system.
第７図に示す半導体集積回路装置は、半導体集積回路チ
ップ１がＡｕ−８ｉ共晶体６で円筒状の放熱フィン９と
セラミック基板２をＡｇろう７で接着して、半導体集積
回路チップ１をセラミックによシパッケージングして構
成される。このような半導体集積回路装置の放熱は放熱
フィン９を前述したと同様な方法で冷却をおこなうが、
冷却装置も含めて装置全体が大きくなシ、高密度化でき
ない欠点がある。In the semiconductor integrated circuit device shown in FIG. 7, the semiconductor integrated circuit chip 1 is made of Au-8i eutectic 6, and a cylindrical radiation fin 9 and a ceramic substrate 2 are bonded together using Ag solder 7. It is composed of various packaging. For heat dissipation of such a semiconductor integrated circuit device, the heat dissipation fins 9 are cooled in the same manner as described above.
The disadvantage is that the entire device, including the cooling device, is large and cannot be increased in density.
以上のように、従来技術による半導体集積回路装置は、
超ＬＳＩの実装を実現するに重要な冷却を高密度実装を
実現しつつ、効率良くおこなうにはまだまだ不十分であ
る欠点を有している。As described above, the semiconductor integrated circuit device according to the conventional technology is
Although cooling, which is important for realizing ultra-LSI packaging, can achieve high-density packaging, it has the drawback that it is still insufficient to perform efficiently.
なお関連技術としては、実開昭５９−１５２７４３号公
報が周知である。Note that as a related technique, Japanese Utility Model Application Publication No. 59-152743 is well known.
本発明の目的は、前述した従来技術の欠点を除去し、高
密度でかつ高い放熱効率が得られる放熱構造を有する半
導体集積回路装置を提供することにある、。SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit device having a heat dissipation structure that eliminates the drawbacks of the prior art described above and provides high density and high heat dissipation efficiency.
この目的を達成するため１本発明は、高密度化を図るた
め１回路形成にのみ用いられていた回路基板に冷却をお
こなうための溝や空洞を設けて冷却媒体を流すようにし
、かつその基板上に半導体チップをその裏面が直接冷却
媒体に接するように実装するととくよシ、冷却システム
を含めた高密度化とすぐれた冷却効率欠得ることのでき
るようにしたことを特徴とする。これによシ、モジエー
ルサイズを従来の数分の１にでき、かつ高い放熱効率を
得ることができる。In order to achieve this object, the present invention provides a circuit board that has been used only for forming one circuit in order to achieve high density, by providing grooves and cavities for cooling to allow a cooling medium to flow through the circuit board. By mounting a semiconductor chip on the top so that its back side is in direct contact with the cooling medium, it is characterized by high density including the cooling system and excellent cooling efficiency. As a result, the module size can be reduced to a fraction of the conventional size, and high heat dissipation efficiency can be obtained.
以下１本発明の実施例を図面を用いて説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第１図は本発明による半導体集積回路装置の斜視図を示
す。第２図、第３図は第１図のＡＡ線の断面における２
つの実施例図である。第４図は回路基板の作成方法を示
している。FIG. 1 shows a perspective view of a semiconductor integrated circuit device according to the present invention. Figures 2 and 3 are 2 in the cross section taken along line AA in Figure 1.
FIG. FIG. 4 shows a method for making a circuit board.
第１図は半導体集積回路チップ１（以下半導体チップ）
を回路基板２に設けた凹状の溝１６に対応させてはんだ
によ〕実装した例である。前記半導体チップ１は側面に
複数個の凹状の接続端子１１を有している。またその裏
面には、基板の溝１６を完全にふさぐだめの封止用メタ
ライズ１４を有している。ここで、凹状の接続端子１１
となる穴はウェーハの段階でレーザ、ドライエッチある
いは化学エッチによシ容易に形成することができる。Figure 1 shows semiconductor integrated circuit chip 1 (hereinafter referred to as semiconductor chip)
This is an example in which the circuit board 2 is mounted with solder in correspondence with the concave groove 16 provided on the circuit board 2. The semiconductor chip 1 has a plurality of concave connection terminals 11 on its side surface. Further, the back surface thereof has a sealing metallization 14 that completely closes the groove 16 of the substrate. Here, the concave connection terminal 11
The holes can be easily formed at the wafer stage by laser, dry etching, or chemical etching.
また、接続端子１１および封止用メタライズ１４は蒸着
あるいはメッキによ！＋、 Ｃｒ−ＣｕあるいはＴｉ−
Ｃｕ−Ｎｉのメタライズ層構成として形成されている。In addition, the connection terminal 11 and the sealing metallization 14 are formed by vapor deposition or plating! +, Cr-Cu or Ti-
It is formed as a Cu-Ni metallized layer structure.
これらのメタライズ１１．１４にはむかえはんだをメッ
キや蒸着によシ形成しても良い。Solder may be formed on these metallizations 11 and 14 by plating or vapor deposition.
一方前記回路基板２は半導体チップに対応させて多数の
凹状の溝１６を設け、それらの間を板状あるいは丸状の
空洞１３で結んだ構造を有している。この溝１６と空洞
１３は第４図に示すように。On the other hand, the circuit board 2 has a structure in which a large number of concave grooves 16 are provided corresponding to the semiconductor chips, and a plate-shaped or round cavity 13 connects the grooves. The groove 16 and cavity 13 are as shown in FIG.
例えば３層の基板を貼合わせることによシ作成する。本
発明ではセラきツク基板を焼成して貼合わせている。ま
た基板の側のメタライズ１２．１４はＡｇ−Ｐｄペース
トの印刷・焼成によるＡｇ−ＰｄメタライズＷペースト
の印刷・焼成後Ｎ１メッキしたＷ−Ｎｉメタライズおよ
び蒸着によるＣｒ−ＣｕあるいはＴｉ−Ｃｕ−Ｎｉメタ
ライズによ多形成される。For example, it is created by bonding three layers of substrates together. In the present invention, ceramic substrates are fired and bonded together. The metallization 12.14 on the substrate side is Ag-Pd metallization by printing and firing of Ag-Pd paste, W-Ni metallization plated with N1 after printing and firing of W paste, and Cr-Cu or Ti-Cu-Ni metallization by vapor deposition. Formed in polymorphism.
このようにして得られる半導体チップ１を回路基板２の
所定の位置にはんだ接続することによシ。By soldering the semiconductor chip 1 thus obtained to a predetermined position on the circuit board 2.
第１図の半導体集積同装置を得ることができる。The semiconductor integrated device shown in FIG. 1 can be obtained.
第２図は第１図のＡＡ’断面図で、半導体チップ１が回
路基板２の凹状溝１６の部分に封止用はんだ１５および
接続用はんた５によシ実装固定されていることを示して
いる。そして形成された空洞に、水やヘリウム等の冷却
媒体を流し、冷却する。FIG. 2 is a cross-sectional view taken along line AA' in FIG. It shows. A cooling medium such as water or helium is then poured into the formed cavity to cool it.
冷却媒体はこの封止用はんだ１５によシ外部にもれない
。また第３図は第２図と同様なＡＡ’断面図で、凹状溝
１６に細い突起１７をセラミックのプレス成形によ多形
成した例を示している。これは冷却媒体に乱流を起こさ
せ冷却効率の向上を図るものである。The cooling medium does not leak to the outside through this sealing solder 15. Further, FIG. 3 is a sectional view taken along the line AA' similar to FIG. 2, and shows an example in which multiple thin protrusions 17 are formed in the concave groove 16 by press molding of ceramic. This is intended to improve cooling efficiency by causing turbulence in the cooling medium.
以上述べたように、本発明は、基板と一体化した冷却方
法と半導体チップの直接ボンディングにより、高密度で
、冷却効率の高いモジー−ルとすることが可能である。As described above, according to the present invention, a module with high density and high cooling efficiency can be obtained by using a cooling method integrated with a substrate and direct bonding of a semiconductor chip.
これは、計算機における演算速度の向上、コストパフォ
ーマンスの良い実装系等を得ることができ、超高速・高
密度計算機システムに寄与する所大である。This makes it possible to improve the calculation speed of a computer and obtain an implementation system with good cost performance, which is the key to contributing to ultra-high-speed, high-density computer systems.
第１図は本発明の斜視図、第２図及び第３図は本発明の
断面図、第４図は本発明の基板作成に関する斜視図、第
５図は従来のフェイスダウンボンディングした半導体集
積回路装置の断面図、第６図は従来技術の第５図の構造
に冷却用の金属棒を押当てた構造の断面図、第７図は従
来技術のセラミックパッケージした半導体集積回路装置
の断面図である。
１・・・半導体集積回路チップ、２・・・回路基板。
１１．１２・・・接続端子、１３・・・空洞、１４・・
・封止用メタライズ、１５・・・封止用はんだ、１６・
・・凹状の溝。FIG. 1 is a perspective view of the present invention, FIGS. 2 and 3 are cross-sectional views of the present invention, FIG. 4 is a perspective view of the substrate fabrication of the present invention, and FIG. 5 is a conventional face-down bonded semiconductor integrated circuit. FIG. 6 is a cross-sectional view of the device; FIG. 6 is a cross-sectional view of a structure in which a cooling metal rod is pressed against the conventional structure shown in FIG. 5; FIG. 7 is a cross-sectional view of a conventional ceramic-packaged semiconductor integrated circuit device. be. 1... Semiconductor integrated circuit chip, 2... Circuit board. 11.12... Connection terminal, 13... Cavity, 14...
・Metallization for sealing, 15...Solder for sealing, 16・
・Concave groove.
Claims (1)
けられた封止用メタライズとを有する半導体集積回路を
、上記接続端子およびメタライズに対応して設けられた
メタライズを有しかつ封止用メタライズから内側に放熱
用冷却媒体が通るための空洞を有する基板にはんだ接続
して構成されたことを特徴とする半導体集積回路装置。A semiconductor integrated circuit having connection terminals provided on the side surface of one element and metallization for sealing provided almost on the outer periphery of the back surface, and a semiconductor integrated circuit having metallization provided corresponding to the connection terminals and metallization for sealing. 1. A semiconductor integrated circuit device, characterized in that it is connected by solder to a substrate having a cavity through which a cooling medium for heat dissipation passes inside metallization.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60217873A JPS6278859A (en) | 1985-10-02 | 1985-10-02 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60217873A JPS6278859A (en) | 1985-10-02 | 1985-10-02 | Semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6278859A true JPS6278859A (en) | 1987-04-11 |
Family
ID=16711107
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60217873A Pending JPS6278859A (en) | 1985-10-02 | 1985-10-02 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6278859A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5146308A (en) * | 1990-10-05 | 1992-09-08 | Micron Technology, Inc. | Semiconductor package utilizing edge connected semiconductor dice |
| JP2007220771A (en) * | 2006-02-15 | 2007-08-30 | Mitsubishi Electric Corp | Semiconductor device and method of manufacturing same |
-
1985
- 1985-10-02 JP JP60217873A patent/JPS6278859A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5146308A (en) * | 1990-10-05 | 1992-09-08 | Micron Technology, Inc. | Semiconductor package utilizing edge connected semiconductor dice |
| JP2007220771A (en) * | 2006-02-15 | 2007-08-30 | Mitsubishi Electric Corp | Semiconductor device and method of manufacturing same |
| JP4617266B2 (en) * | 2006-02-15 | 2011-01-19 | 三菱電機株式会社 | Semiconductor device and manufacturing method thereof |
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