JPS626374A - Vector processor - Google Patents

Abstract

PURPOSE:To prevent the deterioration of performance of a vector processor due to serializing control by adding a means to the vector processor to control the executing order of plural vector instruction elements. CONSTITUTION:When an advanced instruction is executed, a logic circuit produces a valid signal for execution of processing equivalent to a single vector element of the advanced instruction. The subsequent instruction is decoded while said valid signal is processed and therefore a writing counter 201 is cleared to zero. While the valid which executed the 2nd vector element of the advanced instruction is suppressed by a comparator 206. When the processing is through with the 1st element of the subsequent instruction, the valid signal is received through a bus 200 and the counter 201 is counted up. Thus the valid suppression is released and a reading counter 203 is counted up. Then an execution valid signal is obtained on a bus 209.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a vector processing device, and in particular, a method for performing arbitrary main memory references by introducing control that guarantees the order of main memory references for vector elements. The present invention relates to a method for improving the performance of a vector processing device by enabling parallel execution of vector instructions.

[Background of the invention]

Conventionally, various vector processing devices have been proposed in order to perform high-speed processing such as matrix calculations that are frequently involved in scientific and technical calculations. One such vector processing device is a vector processing device that includes a plurality of vector arithmetic units, a vector register, and a requester that transfers data between the vector register and the main memory (Richard M. Russell, rCRAM- 1 Computer System'', General Purpose Large Computer p, 285-295゜Nikkei McGraw-Hill Inc. (1982)). The vector data is once loaded into the vector register by the quester, and later sent to the vector arithmetic unit according to the designation of the vector instruction, processed, and stored in the vector register. If the vector instruction that is subsequently decoded specifies data processing, the vector data on this vector register is sent to the vector arithmetic unit and processed without going through the main memory. In this way, data processing specified by a series of vector instructions is performed via vector registers, which have faster access times than main memory, without going through main memory, so arithmetic units can be designed to be faster than main memory. It has the advantage that it can secure the data transfer capacity necessary for calculations. Furthermore, in order to improve the performance of the vector processing device, the vector register is configured with a high-speed RAM element, and this realizes the function of writing and successively writing to the register at a machine cycle pitch. Technology that parallelizes multiple vector data processing by sending vector elements that have been processed to different vector arithmetic units according to the instructions of the subsequently decoded vector instruction, without waiting for the completion of processing on all vector elements of the instruction. (Japanese Unexamined Patent Publication No. 187828/1983). Hereinafter, the logical operation of simultaneously writing and reading data on vector registers using this technique will be referred to as chaining.

When chaining is performed in a vector processing device,
By sharing the register number written in the operand of an instruction among a plurality of instructions, the ordering among processing elements of a plurality of vector instructions is guaranteed. This sharing of vector register numbers for instruction operands guarantees the order of vector element processing between main memory reference instructions and arithmetic instructions, and between arithmetic instructions. executed by However, the "logic" described by the program is not sufficient to control the chaining operation described above.

For example, with FORTRAN code like this, DOlo
oI-1, N A(I)-B(I)* C(I) D(I)-A(I-1)+ E(I) 10ro C0N
TINUE If the compiler generates object code that simultaneously stores and loads array A, the correctness of the operation cannot be guaranteed.

For example, the compiler output is ■v4cJJ4i4Paj VR04-11■v4cb
41and 7 Rj 4-0■v4eJz4wadu
LpLy V R24-V RO*V R1■v46-
tj4yama4vR2→mu■V+aif4Lyatt y R5←A■v461j
4Ltatl VR44-II v4c, ba, ad
tl V R54-V R5+vR4■v4cJs4J
When a4471j 5-+ 1D, the ordering between elements is not guaranteed between the vector store (■) and the vector load (■). This is because the vector load of ■ may overtake the vector store of ■.

Figure 1 illustrates this overtaking case. Figure 1 divides the processing stage of a vector instruction into a defood stage and an execution stage of each element, and when this division is plotted on the horizontal axis,
This diagram illustrates the one-hour correspondence between the processing stages of the vector store instruction (2) and the vector load instruction (2). In FIG. 1, the locations where vector element numbers are not shown are
This is the stage where the vector instruction (2) cannot be executed.

Unlike arithmetic processing, main memory reference requests are characterized by the irregular appearance of stages in which instructions cannot be executed, as shown in FIG. Due to this unexecutable stage, the processing for the third element of the vector load instruction (2) is being executed even though the processing for the second element of the vector store instruction (2) has not been completed. That is, when I=3 in the second formula of the FORTRAN code, the intended calculation will not be performed.

In order to prevent the inconveniences shown above, conventionally
In many cases, an instruction to perform serial processing is inserted between the vector instructions between and ■, and control is performed to wait for the completion of the vector instruction in ■ and then start execution of the vector load instruction in ■. When such serial rice control is performed, parallel execution of vector instructions is inhibited, and the performance of the processing device is significantly degraded.

[Purpose of the invention]

An object of the present invention is to add a new means to a vector processing device for controlling the execution order among a plurality of vector instruction elements without performing serial rice control between a plurality of vector instructions that make a main memory reference request, and to It is an object of the present invention to provide a vector processing device that can suppress performance degradation of the processing device due to serial rice control.

[Summary of the invention]

In current vector processing devices, chaining operations of the vector processing device are defined by sharing a vector register number as an operand of a plurality of vector instructions. That is, a vector register specified as an operand of a vector instruction specifies a control means that defines the order of operations in addition to a storage means for storing the results of operations. Therefore, between vector instructions that refer to main memory,
Chaining control guarantees the order of data access.

Multiple main memory reference requests are logically decomposed into the following four basic vector instruction pairs.

(1) v4 mountain 4 Jantt V RO, adtt rise a
i 0v4t, JtJ4JLetui v'fi 1a
tlttk*i 1(2) v4da4Jaad V
RD, adtla+, hi 0V46λ54 A
Mu'44 "I R1ndtia,bji 1(3)
v46. te4藷44V RO, adtl浫1jOV
<cJJ+ bad y Rj '-赫ii j(4
) v4a, ty4-i44V RO, --j-h 0
v4c, tr4! 447 Rj, atlda<a
j j.

In the case of (1), there is no need to guarantee ordering between processing elements of two vector load instructions, regardless of whether there is an overlap between addresses 0.1 or not. That is, even if the ordering is guaranteed, the results are not affected.

In the case of (2, 3), if there is an overlap in the addresses of the vector load instruction and the vector store instruction, control is required between the two instructions to ensure ordering between processing elements.

In the case of (4), if two vector store instructions have overlapping at and responses for all processing elements, the previous vector store instruction becomes invalid.

In such a case, the optimization function of the compiler can eliminate the invalid instructions and solve the problem of ordering of processing elements. However, if there is overlap in some of the addresses of two vector store instructions, Funvira cannot solve the problem of ordering of processing elements, and it is necessary to apply hardware chaining control.

In current vector processors, chaining control is often performed in the case of "writing and continuing" to a vector register. Chaining control is possible for any combination of accesses to vector registers, but the number of cases that appear in the program and the control logic are limited.
Due to the balance with the amount of data, chaining control is used in the case of ``writing and writing one after another.''

Consider introducing chaining control to ensure the order of processing elements in cases (2 to 4) of the above examples. First, in case (2), in order to guarantee the order of processing, it is sufficient to use the write enable signal of the vector load instruction to vector register number 0 as the execution valid signal of the subsequent vector store instruction. In case (3), the element write signal to the main memory of the preceding vector store instruction is used as the execution valid signal of the subsequent vector load instruction.

In the case of (4), similarly, the element write signal to the main memory of the vector store instruction may be used as the execution valid signal of the subsequent vector store instruction.

A method of operating a memory requester using such an execution valid signal is a standard feature in current vector processing devices, and this function is used to execute load/store instructions with an index. However, the address of an indexed instruction is data sent from a vector register in synchronization with an execution valid signal, but the method of the present invention differs in that the "address" is generated by an address adder in the quester. Therefore, the execution valid signal does not require data, and the vector register that should hold the valid signal also does not need a data portion. A vector register without such a data part is shown below ■-5can! 7+c
It's called Lulu'Fic Needle-2 (VVR for short). The instruction mnemonic display is shown when this VVR is used to guarantee the order of the elements in the cases (2 to 4) described above.

(2) 746λea, J4ati V RO,
atlia, c*jO, V V R0v4c, te4z
M147 R1, adtt44jj1, V V R
O.

(3) v0Ω)h 6A4V RO, cLtld
44*a O, V V R0v4tslz4J-taj
V R1, attd 赫*i 1, V V RO.

(4) v4c, λ14 Lum A4V RO, atlt
tru number *, h O, V V R0v4cily4j+
M14V R1, ndtta<i* 1,'I V
R.O.

Next, if the subsequent instruction is a vector store instruction,
Store data sent from the vector register and VV
Consider synchronization with the execution valid signal sent from R. Since chaining control of vector registers and VVR cannot be used to achieve this synchronization, a stack of store data and execution valid data is provided in the memory requester, and by controlling this stack, chaining control of vector registers and VVR can be used. Performs control to interrupt the inning.

In the above discussion, an attempt has been made to solve the problem of the ordering of processing elements for a main memory reference request of a two-vector instruction from the viewpoint of vector register chaining control. However, from the viewpoint of a means for reporting the processing status of vector instructions, the control using the VVR described above means that the earlier issued instruction controls the execution of the later issued instruction. Therefore, the above-described control using VVR does not exceed the range of data processing possible with vector processing devices employing conventional vector register control methods.

In order to surpass the data processing of conventional vector processing devices, a control means is required in which the processing of later instructions defines the processing of earlier instructions. An example that requires control in the opposite direction to the control direction of conventional instructions is the FORTRAN code T
R state, DOlooI-1,NA(LISTl(I))-A(LIST2(I))
+1.01oo C0NTINUE. In this example, the execution order of loading and storing for the array person is Load → Store → Load → Store → ...
・It must be done mutually as follows. Therefore array A
It is necessary to synchronize the process of storing the calculation result into the vector register using the load instruction with index and the process of writing the calculation result to the main memory using the store instruction with index. This synchronization means is a "control means by which later instructions specify the processing of earlier instructions."
can be used.

By expanding the control method using VVR in this way, vector processing can also be applied to processing that is impossible with vector register chaining control.

In order to distinguish the above-mentioned recursive control using VVR from the VVR chaining control described above, the mnemonic of the command is expressed as 'PATH'. According to this display, the object code is like the FORTRAN code TR format described above.

■v4c, tea, Jeaj VROh L I
S T 1■v4bb+ Lead V R14-
L Eng S'I'2■ V<a&ru Jaad Lrut<r
-ul V R24-A, swLtcy L engineering S T
2, PATHO■v4!4d false--j4adtlV
R54-V R2+'t O'■ -1) a,, *λI
v4Lrw14-V R34A, vaLng LIS
Tl, PATHO.

That is, a causal relationship is set between the indexed load instruction (2) and the indexed store instruction (2) under the control of the VVR, resulting in the following processing.

First, the load command with index in ■ is executed, and the first
Vector elements are stored in VR2.

At the next timing, the element in question is processed by the vector addition instruction (3) and the result is stored in VR3. Next, the operation result on VR3 is stored in the A array on the main memory by an indexed store instruction. After the store operation is completed, the completion of processing of one element of the vector instruction (2) is reported to the memory requester executing the indexed load instruction (2) through VVR control. According to this report, the second element of array A is loaded into ■R2 by the instruction ■. As above, ■, ■.

Synchronization is established between the vector instructions of
The correctness of AN code processing is guaranteed by the vector processing device.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described using FIG. 2.3.4.

FIG. 2 shows a schematic block diagram of the vector processing device of the present invention, where 1 is a vector register, 2 is an arithmetic unit, and 3 is a VV
R and 4 are initial value set logic units, 5 and 6 are memory requesters, 7 and 9 are switching circuits, 8 is a main memory having an interleaved configuration, and 10 is a switching circuit that connects paths by vector instructions.

Consider a case where a vector processing device is activated, data processing is performed, a load instruction and a store instruction are simultaneously executed in parallel, and accesses of both instructions overlap on the main memory. This duplication can be detected by the compiler. When a preceding vector load instruction is executed, path combinations are performed according to the information defined in the operand fields of the instruction. Here, the memory requester 5 is activated by the load instruction, the paths 20 and 21 are connected by the switching circuit 11, and the data bus 22 from the main memory 8 is associated with the vector register write path 23 by the switching circuit 9. do. here"
"Compatible with" means that the data on the data bus from the main memory is classified according to which memory requester is the main memory reference request, and the data is written to a vector register for the purpose of only data for a specific memory requester. It means sending to the path. When execution of the vector load instruction is started, a main memory reference address is generated inside the memory requester 5.

FIG. 5 is a schematic block diagram of the memory requester 5. As shown in FIG.

When the memory requester is activated, the base value of the array is set in a latch in the counter 101 through path 100. At the same time, an increment value for pointing to the array is set in register 103 via path 102. Next, in response to the "execution valid signal" sent through the path 104, the base value and the value of the increment register are added by the counter 101, and the result is set in the register 105 to generate an address. The address on register 105 is sent via path 106 to switching circuit 7 (FIG. 2).

The switching circuit 7 in FIG. 2 checks the sent address, determines in which bank of the main memory 8 the address is located, selects one of the paths 24, and sends a request signal to the main memory. . At this time, a tag is added to the request signal to distinguish it from request signals from other memory requesters. Additionally, a storage signal is added to distinguish between stores and loads. The main storage device 8 sends data and tags to the path 22 in response to the request signal. Switching circuit 9 sends data to the specified vector register write path 23 using the tag.

On the other hand, if control using VVR is described in the operand of the instruction, the memory requester sends a valid signal via the path 20 every time it generates an address. The signal passes through the path 21 and via the selector 13, and increments the write counter of the VVR indicated by the instruction operand by one.

FIG. 4 shows a schematic block diagram of the VTR.

In FIG. 4, when a valid signal is sent through path 200, write counter 201 starts counting.

Will be uploaded. It is assumed that the register 202 stores this count-up value. It is assumed that the write counter 201 is cleared to zero when the instruction is decoded by the vector processing device.

Chaining control via VVR is performed as follows. When the instruction to read the VVR is decoded, the read counter 203 is cleared to zero.

Next, a clock signal from the timing generator is received via a path 204, and a read counter 203 is counted up via an AND circuit 205. The contents of the read and write counters are constantly compared by a comparison circuit 206, and when the value of the successive counter 203 becomes equal to the value of the write counter 201, a signal is sent onto the bus 207 to suppress the count up of the successive counter 203. The signal is logically ANDed with the clock signal by the AND circuit 205 via the inverter 208, and the operation of the successive counter 203 is interrupted. Path 210 is used when it is desired to interrupt reading of the VVR due to an external factor. When the value of the read counter 203 is smaller than the value of the write counter 201, the comparison circuit 206 sends out a valid signal onto the bus 209 in synchronization with the signal that counts up the read counter 203.

Execution control of the subsequent instruction with respect to the preceding instruction via the VVR is performed as follows. When the preceding instruction that performs the control is executed, the logic circuit 4 in FIG. 2 generates a valid signal so that one vector element of this instruction is processed.

While this valid signal is processed, the subsequent instruction is decoded, so the write counter 201 is cleared to zero, and the valid signal for executing the second vector element of the preceding instruction is detected by the comparison circuit 206 in FIG. is suppressed by. When the processing of the first element of the subsequent instruction is completed, a valid signal is received through the path 200, and the write counter 201 is counted up. As a result, the suppression by the comparison circuit 206 is released, the read counter 203 counts up, and an "execution valid" message is displayed on the path 209.
I get a signal.

Returning to FIG. 2, chaining control via VVR will be explained. Assume that the preceding vector load instruction and vector store instruction are chained via a VTR, and the memory requester 5 executes the vector load instruction, and the memory requester 6 starts executing the vector store instruction. Prior to the start of this vector store instruction, when decoding the instruction, the vector register 1 and the path 25 for transferring store data are coupled, VVRl, ! :
Data path 26 is coupled via selector 14 . Further, the path 26 and the path 27 are coupled by the switching circuit 10. After the above combination is completed, the memory requester 6 is activated. Here, a main memory reference control method when two or more memory requesters are operating will be described.

If two or more memory requesters are running at the same time,
By chance, main memory reference requests from both requesters may point to the same bank. At this time, a priority order is determined between each memory requester, and control is thereby made such that the main memory reference request of the other memory requester is made to wait, and the reference request is accepted after access to the bank in question is completed. This main memory reference request ranking determination and delay control logic is collectively called priority logic, and is a well-known control method.

In FIG. 2, the logic concerned is deleted to simplify the drawing. However, referencing main memory via priority logic is equivalent to not being able to generate addresses in the memory requester and transfer store data from vector registers to machine cycle pitches. Therefore, FIG. 2 shows operation interruption instruction buses 2B, 29, 30, and 31 to the memory requester and vector register. When a main memory reference is interrupted by a vector load instruction using these paths, the address generation of the requester 5 is interrupted via path 28. In the case of a vector store instruction, the path 28 interrupts address generation, and the path 50 interrupts the successive reading of the vector register 1.

Assuming that the memory requester of at is operating as described above, the case where a store instruction is processed by the memory requester 6 under the control of the VVR will be described with reference to FIG.

In FIG. 3, 108 is an up/down counter;
9 is a store data stack, path 25α is a path for a command signal indicating that store data has been sent, and 254 is a data bus for path 25α. (In FIG. 2, both buses 25α and 4 are collectively referred to as path 25.

) When an execution valid signal is sent from the VVR via the path 27, the up/down counter 108 is decremented by 1.

When a store data command is sent via the path 25α, the up/down counter 108 is incremented by 1.

Here, let the number of stages of the store data stack be le. The up/down counter 108 sends out a valid signal on the path 104 at the machine cycle pitch while the counter value is in the range from 1 to +1.

When the counter value becomes 0 or less, a signal to inhibit VVR reading is sent onto the path 31α. Further, when the counter value becomes +1 or more, a signal instructing to suppress successive generation of vector registers is sent to the path 31.

When a main memory reference request is made to wait in the main memory device due to the priority logic, a memory requester operation interruption instruction signal is sent via the path 29. This signal interrupts the up/down counter 108 and causes the path 10 to stop counting.
4, the operation of the read counter 101 is interrupted. At the same time, through paths 31α and 4, the vector register, VVR
interrupt the operation. As described above, read synchronization between the VTR and the vector register is achieved. Under the above synchronization control, the store data is on path 107, f, and the address is on path 1
06. In Figure 2, this path is 32,5
It corresponds to 5.

Next, the operation when the operation of the preceding vector instruction is controlled by the later vector instruction will be explained with reference to FIG. Assume that the preceding vector instruction is a load and is processed by memory requester 5. When the vector instruction decoder of the vector processing unit detects a PATH specification and activates a vector instruction with a PATH specification, it activates switching circuit 10 through path 34 and couples paths 35 and 36.

This combination is performed only during the processing timing of the first vector element when the initial value set logic unit 4 operates. After the second vector element, paths 37 and 36 are combined.

Assuming that the subsequent vector instruction is processed by memory requester 6 and is a store instruction, paths 38 and 39 are then coupled by switching circuit 12.

In the preceding vector load instruction, an address for one vector element is generated based on the valid value generated by the initial value set routine 4, and a main memory reference request is sent to the path 106. At the next timing, no valid data is sent from the VVR through paths 37 and 36, so processing for the second vector element is not started. However, the main memory reference request for the first vector element becomes load data via the main memory 8 and the switching circuit 9, and the data is written into the vector register 1 via the path 23.

If there is an arithmetic instruction between the preceding vector load instruction and the subsequent vector store instruction, the data will be passed to pass 4G.
, the arithmetic unit 2, and the path 41 to obtain the operation result, which is written into the vector register 1. The calculation result is pass 25
The data is sent to the memory requester 6 via the memory requester 6. The memory requester processes the store instruction for one vector element, and sends the store address and data onto paths 32 and 33. At the same time, a valid signal is sent on the path 38 indicating that processing for one vector element has been completed. This valid is sent to the write counter 2 of the VVR via path 39.
Add 1 to the value of 01. As a result, the value of the VVR successive counter 203 is incremented by 1, and a valid signal is sent onto the path 37. By performing the above processing cyclically, it becomes possible to synchronize the processing of the preceding vector load instruction with the vector store instruction described later.

In this example, for simplicity, a combination of a vector load instruction and a vector store instruction has been described, but synchronization can also be performed using a similar process with a combination of a load instruction with an index and a store instruction with an index. In this case, the index and store data are synchronized by chaining operations of vector registers. Furthermore, combinations of vector store and load instructions and mutual combinations of vector store instructions are also possible by changing the combination of paths using the switching circuits 10, 11 and 12.

In FIG. 2, the number of interleaps in the main memory is 4 and the number of memory requesters is 2, but these numbers are specific numbers for the purpose of simplifying the explanation, and these numbers themselves have no particular meaning.

〔Effect of the invention〕

According to the present invention, in a vector processing device, it becomes possible to synchronize each vector element using VVR for any pair of vector instructions that do not share a vector register number. This synchronization control makes it possible to guarantee the processing order of elements for any pair of read and write instructions that refer to the main memory. By guaranteeing the processing order, it becomes possible to execute in parallel a process in which a conventional vector processing device inserts an instruction to perform serialization between vector instructions whose processing order must be guaranteed. In addition, a pair of main memory reference instructions including indirect addressing, which could not be vector-processed by conventional vector processing devices, can be processed by vector processing by synchronously controlling the execution of the subsequent vector instruction and the execution of the preceding vector instruction. becomes possible. As described above, it is possible to improve the parallel processing performance of the vector processing device and improve the performance.

[Brief explanation of drawings]

FIG. 1 is a processing diagram of a main memory reference vector instruction, FIG. 2 is a schematic block diagram of the synchronization control section of the vector processing device based on the present invention, FIG. 3 is a schematic block diagram of the memory requester, and FIG.
The figure is a VVR schematic block diagram. In FIG. 2, 1... Vector register, 2... Arithmetic unit, 3- VL-smj V<, dzc R<$Al4h
(V VR), 5.6...Memory requester 1. 7,9,11.12...Switching circuit, 8...
・Main memory. In FIG. 3, 101...counter, 108...up/down counter, 109...store data stack. In FIG. 4, 201...Write counter, 203...Read counter, 205°A N D circuit 1
．． 2゜Representative Patent Attorney Katsuo Ogawa Figure 1 Unexamined Patent Publication No. 30 Figure 2

Claims (1)

[Claims] A main storage device, a plurality of vector registers, a plurality of data transfer circuits that transfer data between the main storage device and the vector registers, and perform arithmetic processing on the vector data received from the vector registers and output the results. In a vector processing device that is equipped with a plurality of vector arithmetic units that send data to the vector register and processes vector instructions, chaining control via the vector registers is different from chaining control to virtual registers that do not have data. A control means, a means for coupling the control means and a signal indicating a processing state of a vector instruction that refers to the main storage device, and a combination of the means is specified in a field of the vector instruction, and these means are combined. A vector processing device characterized in that the processing order of vector elements can be guaranteed for any pair of main memory reference vector instructions.