JPS6259485A - Character broadcasting receiver - Google Patents

Abstract

PURPOSE:To make both broadcasting pictures legible and simultaneously enjoy both programs by reducing the character broadcasting screen to a smaller size than an original display size and displaying and simultaneously displaying a TV broadcasting picture on a remaining part. CONSTITUTION:A TV signal channel-selected by a tuner 4 of a receiver is amplified and detected in a video amplifier circuit 6 to output a composite video signal. In a video signal processing part 8, a TV video signal is separated from the video signal, the signal is added to a CRT 18 through a video change over circuit 12, a video output circuit 14 and a synchronous signal from a synchronous signal processing part 10 is added to a deflection coil 16. Further, a character broadcasting signal is sampled in a character signal processing part 20 and the character broadcasting signal is converted into a character display signal. The character display signal from the processing part 20 is stored in a display memory 22 and an address of the character information stored in the memory 22 is designated by column and line address counter parts 24, 26. In a system control part 40, the respective parts are controlled and the reduced character broadcasting picture and a TV broadcasting screen are easily seen and simultaneously displayed.

Description

Detailed Description of the Invention Technical Field> The present invention extracts a teletext signal superimposed on a television video signal, stores text information data based on the extracted teletext signal in a display memory, and displays the output on a CRT. The present invention relates to a teletext receiver that displays a teletext screen on a TV.

<Prior art> Display formats for teletext programs include those in which the teletext screen is displayed on the entire display screen of a CRT, and the so-called superimposition display in which the teletext screen and a normal television broadcast screen are displayed in double projection. There are some shown. In the former case, since the television broadcast screen cannot be displayed while the teletext screen is displayed, the user may miss the progress of the television broadcast program and cannot fully enjoy the program.

In the latter case, the television broadcast screen and the teletext screen are displayed at the same time, so there is no drawback like the former, but with conventional teletext receivers, the television broadcast screen and the teletext screen are displayed double. There is a problem in that both screens are difficult to see because they are displayed as .

<Object of the Invention> The present invention has been made in view of the above-mentioned problems, and it is possible to display a teletext screen in a smaller size than the original display size, and simultaneously display a television broadcast screen in the remaining part. To make it possible to display both a teletext screen and a television broadcast screen so that both programs can be easily viewed and to enjoy both programs in parallel.

<Structure of the Invention> In order to achieve the above-mentioned object, the present invention includes a display memory that stores a teletext signal extracted from a composite video signal as text information data, and a column address counter section that specifies a column address for this display memory. In a teletext receiver equipped with a row address counter unit for specifying a row address, a reference oscillator outputs a clock pulse of a predetermined frequency to the column address counter unit, and the clock pulse of this reference oscillator is divided in frequency. The column address counter section is connected to the frequency divider via a clock pulse switching circuit that switches these outputs, while the column address counter section is configured to switch the lowest pit of the read address for the display memory for each field scan to specify the lowest pit. a specifying means;
and a counter that counts clock pulses synchronized with a horizontal synchronizing signal and designates bits higher than the least significant hit.

<Example> Hereinafter, the present invention will be described in detail based on an example shown in the drawings.

FIG. 1 is a block diagram of a teletext receiver according to an embodiment of the present invention. In the figure, reference numeral 1 indicates the entire teletext receiver, 2 an antenna for receiving a television signal on which a teletext signal is superimposed, 4 a tuner for tuning the television signal received by the antenna 2, 6 is a video amplification circuit that amplifies and detects the television signal selected by the tuner 4 to extract a composite video signal; 8 is a video signal processing unit that separates the television video signal from the composite video signal; 1
0 is a synchronization signal processing unit that separates a synchronization signal from a composite video signal, and I2 is an image that switches between a television video signal obtained by the video signal processing unit 8 and teletext information data read from a display memory 22, which will be described later. 14 is a video output circuit, 16 is a deflection coil, and 18 is a CRT.

The television signal selected by the tuner 4 is amplified and detected by the video amplification circuit 6, and a composite video signal is extracted.

The video signal processing unit 8 separates the television video signal from the composite video signal, and this television video signal is applied to the video output circuit 14 from one individual contact +2b of the video switching circuit 12 via the common contact 12a, and is amplified. After that, CR
It is output at T18. Further, the synchronization signal processing section 10 separates the synchronization signal from the composite video signal, and the synchronization signal is
The signals are applied to the deflection coil 16 of T18 as horizontal and vertical drive signals.

Reference numeral 20 denotes a character signal processing unit that extracts the teletext signal superimposed on the composite video signal and converts the extracted teletext signal into a character display signal; 22 represents a character display signal output from the teletext signal processing unit 20; 24.26 is a display memory 22 that stores 24.26 as character information data.
A row address counter section and a column address counter section 28 designate read addresses of rows and columns of character information data stored in the display memory 22, respectively, and 28 switches address designation signals when writing or reading character information data to or from the display memory 22. This is a first switching circuit.

The teletext signal processing section 20 extracts the teletext signal from the composite video signal, converts the extracted teletext signal into a character display signal, and then sends it to the display memory 22. At this time, since the teletext signal processing unit 20 provides an address designation signal to the display memory 22 via the first switching circuit 28, the character display signal is stored as character information data at the address designated position. When reading character information data from the display memory 22, the common contact 28a of the first switching circuit is connected to the other individual contact 28c, and the row,
Address designation signals output from column address counter sections 24 and 26 are applied to display memory 22. The character information data read out by specifying the address is sent to the video switching circuit 1.
The signal is applied from the other individual contact 12c of 2 to the video output circuit 14 via the common contact 12a.

30 is a predetermined frequency (in this example, frequency r2-2 f, which is twice the frequency f1 corresponding to the full screen display width of CRT1B)
32 is a frequency divider that divides the clock pulse of this reference oscillator 30 by l/2; 34 is a clock pulse switching circuit that switches the output of the reference oscillator 30 and the frequency divider 32; The switching operation of this clock pulse switching circuit 34 is performed by the system control unit 4, which will be described later.
It is controlled by a control signal Sc from 0.

36 is a selection switch operated to select whether to display the teletext screen on the entire screen of the CRT 18 or in a reduced size; 38 is a control signal Sc outputted from the system control unit 10, which will be described later. This is a field discriminating section that outputs a field scanning discriminating signal sb whose level is alternately inverted in response to the vertical synchronizing signal V from the synchronizing signal processing section IO.

Then, the field scanning discrimination signal sb output from the field discrimination section 38 is applied to the second address counter section 26.

40 is a column address counter section 26, a row address counter section 26, a video switching circuit 12, and a clock pulse switching circuit 3.
4 and the field discrimination section 38. Then, the system control section 40 outputs a clock pulse Sa in response to the horizontal synchronization signal H output from the synchronization signal processing section IO, and this clock pulse Sa is given to the row address counter section 26.

FIG. 2 is a detailed block diagram of the row address counter section 26. This column address counter 26 is connected to the display memory 22.
Least significant bit A of the read address for. The least significant bit designating means 42 switches and designates the least significant bit A for each field scan, and the least significant bit A is counted by counting clock pulses Sa synchronized with the horizontal synchronizing signal H. , and a counter 44 for specifying higher-order bits A, .about.An. In this example, the least significant bit designation means 42 is
a frequency divider 46 that divides the frequency of the clock pulse Sa by l/2;
It is comprised of a second switching circuit 48 that switches between the clock pulse Sa and each output of the frequency divider 40, and an OR circuit 50 that inputs both the output of the frequency divider 46 and the field discrimination signal sb. 52 is an input terminal for the clock pulse Sa output from the system control unit 40; 54 is the field determination unit 3;
an input terminal for the field discrimination signal sb output from 8;
56 is a control signal Sc output from the system control unit 40
This is the input terminal of The operations of the frequency divider 46 and the second switching circuit 48 are controlled by the control signal Sc given from the system control section 40.

Next, regarding the teletext receiver l having the above configuration,
The operation when a teletext screen is displayed on the screen of the CRT 18 will be explained with reference to FIGS. 3 and 4.

When displaying a teletext screen, the common contact 28a of the first switching circuit 28 is connected to the other individual contact 28c. next,
As shown in Figure 3(a), the teletext screen is displayed on a CRT18.
When displaying on the entire screen, when the selection switch 36 is turned off, the system control section 38 responds by sending a control signal Sc to the clock pulse switching circuit 34, row address counter section 26, and field discrimination section 38, respectively. Output.

As a result, the common contact 3 of the clock pulse switching circuit 34
4a is connected to one individual contact 34b, and the common contact 48a of the second switching circuit 48 of the row address counter section 26 is connected to one individual contact 48b, and the frequency divider 46 becomes operational, and the field The operation of the determining unit 38 is stopped. Therefore, the field discrimination signal sb output from the field discrimination section 38 is always at a low level.

Next, the system control section 40 once clears the count of the column address counter 24 in response to the horizontal synchronization signal H given from the synchronization signal processing section 10. Subsequently, the frequency f2 of the clock pulse output from the reference oscillator 30 is divided by 1/2 by the frequency divider 32, and the divided clock pulse is sent to the clock pulse switching circuit 34.
The address is given to the column address counter section 24 via the column address counter section 24. The column address counter section 24 counts up and specifies the column address of the display memory 22 every time the frequency-divided clock pulse is applied. In this case, the frequency f of the clock pulse divided by the frequency divider 32 corresponds to the full screen display width of the CRT 18, so the reading speed of character information data from the display memory 22 in the column direction is Matches the horizontal dimension of the display screen.

On the other hand, the clock pulse Sa outputted from the system control unit 40 in synchronization with the horizontal synchronization signal H is frequency-divided by the divider 46 of the row address counter unit 26, and the frequency-divided output is input to one side of the OR circuit 50. It is applied to the counter 44 via the second switching circuit 48.

At this time, since the field discrimination signal sb applied to the other input terminal of the OR circuit 50 is always at a low level, the output from the frequency divider 46 is the lowest bit V of the row address for the display memory 22. This is an addressing signal that indicates. Further, the counter 44 counts up every time a clock pulse from the frequency divider 46 is applied, and its output is sent to the display memory 22 as the least significant bit (2). This is an address designation signal that designates bits v1 to Vn of higher order digits.

FIG. 4 is an explanatory diagram showing the relationship between row address designation of the row address counter unit 26 for the display memory 22 and field scanning. Figure (a) shows the case of full-screen display, with solid lines corresponding to numbers 1 to 13 in the figure showing the display in the case of one field scanning, and broken lines corresponding to numbers B to 13° indicating the next screen. The display for field scanning is shown.

As mentioned above, row addressing for the display memory 22 starts from the lowest point (V). is a signal generated based on a clock pulse Sc synchronized with the horizontal synchronizing signal H, and repeats level inversion in synchronization with the output of the frequency divider 46. Further, the more significant bits A, -An are counted up every two horizontal scanning lines. Therefore, if one field is scanned and row addresses are sequentially specified in the order of numbers 1 to 13, then in the next field scan, row addresses are sequentially specified in the order of numbers B to 13°. In this case, since the order of addressing in the previous field scan and the next field scan is exactly the same, character information data with the same content will be read from the display memory 22.

In this way, the teletext screen is displayed on the entire screen of the CRT 18.

Next, as shown in FIG. 3(b), if the teletext screen is to be reduced and displayed and the remaining portion is to be displayed as a television broadcast screen, the selection switch 36 is turned on. When the selection switch 36 is turned on, the system control unit 40 responds to this by transmitting the control signal SC to the clock pulse switching circuit 34.
, row address counter section 26 and field discrimination section 3
8 respectively. As a result, the common contact 34a of the clock pulse switching circuit 34 becomes the other individual contact 34c, and the second switching circuit 48 of the row address counter section 26
The common contact 48a is connected to the other individual contact 48c, and the operation of the frequency divider 46 is stopped. Further, the field discrimination unit 38 becomes deaf in its operable state.

Therefore, the system control unit 40 controls the synchronization signal processing unit 1
The count of the column address counter 24 is completely cleared in response to the horizontal synchronization signal H given from 0, and then the clock pulse from the base ω oscillator 30 is applied to the column address counter 26 via the clock pulse switching circuit 34. Since the frequency r of the clock pulse of the reference oscillator 30 is set to twice the frequency in the case of full-screen display, character information data is sent from the display memory 22 in the row direction as compared to the case of full-screen display. Reads in half the time.

Therefore, the horizontal display size of the teletext display screen is 1/2 that of full-screen display.

On the other hand, from the field discrimination section 38, the synchronization signal processing section 10
In response to the vertical synchronizing signal (2) from the field scanning signal sb, a field scanning discrimination signal sb for controlling level inversion is output. This field discrimination signal sb is applied to one input terminal of the OR circuit 50 of the row address counter section 26. At this time, since the other input terminal of the OR circuit 50 is always at a low level, the field discrimination signal sb is the least significant bit (■) of the row address for the display memory 22. This is an addressing signal that indicates. Therefore, the least significant bit A. The level is reversed every field scan, such that if it is high level in one field, it is low level in the next field. Further, the clock pulse Sa outputted from the system control unit 40 in synchronization with the horizontal synchronization signal H is the second clock pulse Sa.
The signal is applied to the counter 44 via the switching circuit 48. Therefore, the counter 44 counts up every time the clock pulse Sa is applied, and its output is sent to the display memory 22 as the least significant bit V. Bits of higher order digits than ■1~Vn
This is an addressing signal that specifies the address.

As a result, the row address counter section 26 as a whole has 1
A count-up operation is performed at every row address.

FIG. 4(b) shows the case of reduced screen display, and shows the display in the case of one field scanning in which there are solid lines corresponding to numbers 1 to 7, and broken lines corresponding to numbers B to 6. The display for field scanning is shown.

As described above, as a result of the row address counter section 26 counting up every row address device, half of the character information data stored in the display memory 22 is read out in one field, and the remaining half is read out in the next field. Character information data is read.

Therefore, the vertical display dimension of the teletext display screen is I/2, and as mentioned above, the horizontal dimension is also 1/2.
Since the teletext screen is compressed to 1/4, the entire teletext screen is displayed reduced to 1/4. After the character information data is read from the display memory 22, the system control unit 40 changes the common contact 12a of the video switching circuit 12 to one individual contact +2.
b, so that the television broadcast screen is displayed on the remaining portion of the display screen of the CRT 18.

In this embodiment, the frequency of the reference oscillator 30 and the counter 44 are set so that the display size when the teletext screen is reduced and displayed is 1/2 in both the horizontal and vertical directions. The present invention is not limited to this, and it is also possible to change the compression width of the teletext screen in several steps.

<Effects of the Invention> As described above, according to the present invention, the teletext screen is displayed in a smaller size than the original display size, and the remaining portion can be simultaneously displayed with the television broadcast screen. Both the broadcast screen and the television broadcast screen become easier to see, and since it is no longer possible to miss the television broadcast program while watching the teletext program, it becomes possible to enjoy both programs.

[Brief explanation of the drawing]

The drawings show an embodiment of the present invention. FIG. 1 is a block diagram of a teletext receiver, FIG. 2 is a detailed block diagram of a row address counter of the teletext receiver, and FIG. 3 is a teletext display image. FIG. 4 is an explanatory diagram showing the relationship between address designation for the display memory and field scanning. 1. Teletext receiver, 22. Display memory, 24. Column address counter section, 26. Row address counter section, 30. Basic oscillator, 32. Frequency divider, 34. Clock pulse switching. Circuit, 42...Least significant bit designating means, 44...Counter.

Claims (1)

[Claims] (1) A display memory that stores a teletext signal extracted from a composite video signal as text information data, a column address counter section that specifies a column address for this display memory, and a row address counter section that specifies a row address are provided. In the teletext receiver, the column address counter unit is provided with a clock pulse switching unit that switches between a reference oscillator that outputs clock pulses of a predetermined frequency and a frequency divider that divides the clock pulses of this reference oscillator. The column address counter section includes a least significant bit designating means for switching and designating the least significant bit of a read address for the display memory for each field scan, and a clock pulse synchronized with a horizontal synchronizing signal. A teletext receiver comprising: a counter that counts and specifies bits higher than the least significant bit.