JPS6257345A - Frame check sequence system - Google Patents

Frame check sequence system

Info

Publication number
JPS6257345A
JPS6257345A JP60196388A JP19638885A JPS6257345A JP S6257345 A JPS6257345 A JP S6257345A JP 60196388 A JP60196388 A JP 60196388A JP 19638885 A JP19638885 A JP 19638885A JP S6257345 A JPS6257345 A JP S6257345A
Authority
JP
Japan
Prior art keywords
frame check
check sequence
data
frame
fcso
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60196388A
Other languages
Japanese (ja)
Inventor
Shuhei Arima
有馬 秀平
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP60196388A priority Critical patent/JPS6257345A/en
Publication of JPS6257345A publication Critical patent/JPS6257345A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To reduce the relay time by applying frame check sequence in the stage of the reception of an FCSO after a header in data relaying so as to complete the next sending preparation during the reception of the succeeding data. CONSTITUTION:Two FCS (FCSO and FCSI) are used. The FCSO applies the frame check sequence to the heater H and the FCSI applies the frame check sequence to all frames. Thus, at the relay station side, the frame check sequence is applied immediately when the FCSO is received to confirm the destination and sender. When the FCSO is received and the frame check sequence is finished (when a transmission D is received), the preparation of transmission to the next reception station is applied and when the reception of the data D and the frame check sequence by the FCSI are finished, the data is sent immediately.

Description

【発明の詳細な説明】 〔概要〕 データ伝送を行う場合、通信制御装置に文字組立/分解
部とチャンネル部の間にあって固定長の最初の文字列の
フレームチェックを行い、チャンネル部に報告する機能
を有するフレームチェックシーケンス用付加装置を付加
する。
[Detailed Description of the Invention] [Summary] When performing data transmission, the communication control device has a function that is located between the character assembly/disassembly unit and the channel unit and performs a frame check on the first character string of a fixed length, and reports the result to the channel unit. An additional device for frame check sequence is added.

〔産業上の利用分野〕[Industrial application field]

本発明はデータ伝送に関するものである。 The present invention relates to data transmission.

従来のフレームチェックシーケンス方式によるとデータ
の中継を行う場合伝送時間が長くなると云う欠点があり
、此の改善が強く要望されていた。
The conventional frame check sequence method has the disadvantage that it takes a long time to transmit data when relaying data, and there has been a strong demand for an improvement.

〔従来の技術〕[Conventional technology]

第4図は従来の伝送フレームの一例を示す。 FIG. 4 shows an example of a conventional transmission frame.

図中、Fはフラグ、Hはヘッダ、Dはデータ、Fe2は
フレームチェックシーケンスである。
In the figure, F is a flag, H is a header, D is data, and Fe2 is a frame check sequence.

フラグFは伝送フレームの最初又は最後を表す特定ビッ
ト列であり、例えば8ビツトで構成される。ヘッダHに
は宛先、発信元等が格納され、普通固定ピント長である
。フレームチェックシーケンスFC’Sは受信局が伝送
誤りを検出する為の一連のビット列であり、本例では1
6ビツト構成である。データDは電文である。
Flag F is a specific bit string representing the beginning or end of a transmission frame, and is composed of, for example, 8 bits. The header H stores the destination, source, etc., and usually has a fixed focus length. The frame check sequence FC'S is a series of bit strings used by the receiving station to detect transmission errors.
It has a 6-bit configuration. Data D is a telegram.

従来データ伝送を行う場合のフレームチェックシーケン
ス方式は第4図に示す様に固定パターンで挟まれたデー
タ列全てに就いて、即ち、一つの伝送フレームに対して
チェックを行っていた。
In the conventional frame check sequence method for data transmission, as shown in FIG. 4, all data strings sandwiched between fixed patterns are checked, that is, one transmission frame is checked.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

従って二点間で上記伝送フレームで構成される信号を使
用して通信を行い、其の正常性を確認する場合は良いが
、此の信号を更に中継して次局へ送出する場合には、−
伝送フレームを受信し、其のチェックを終了しなければ
次の発信動作に移れない事になる。従って中継に要する
時間がかかると云う欠点があった。
Therefore, it is good to communicate between two points using a signal made up of the above transmission frame and check its normality, but when this signal is further relayed and sent to the next station, −
Unless the transmission frame is received and its check completed, it is not possible to proceed to the next transmission operation. Therefore, there is a drawback that the relay takes time.

本発明の目的は此の中継時間の短縮を図り且つ同等レベ
ルのフレームチェックシーケンス方式を提供することで
ある。
An object of the present invention is to shorten this relay time and provide a frame check sequence system of the same level.

Fe2Oを付加したフレームを使用し、フレームチェッ
クシーケンス方式を採る通信制御装置の構成を回線毎の
文字組立/分解部50〜5N、文字組立/分解部50〜
5、に於いて組立られた受信文字と、分解されて送信さ
れる文字をメモリ2との間で転送制御するチャンネル部
3、及び文字組立/分解部50〜5Nとチャンネル部3
の間にあって固定長の最初の文字列のフレームチェック
を行い、チャンネル部3に報告する機能とチャンネル部
3からの送信データの固定長の最初の文字列にフレーム
チェックデータを付加する機能を有するフレームチェッ
クシーケンス用付加装置4を具備することにより解決さ
れる。
The configuration of a communication control device that uses frames with Fe2O added and adopts a frame check sequence method is as follows: character assembly/disassembly units 50 to 5N for each line, character assembly/disassembly units 50 to 5N, and character assembly/disassembly units 50 to 5N for each line.
5. A channel section 3 that controls the transfer of the received characters assembled in step 5 and the disassembled and transmitted characters between the memory 2 and the character assembly/disassembly sections 50 to 5N and the channel section 3.
A frame that is located between the frames and has a function of performing a frame check on the fixed-length first character string and reporting it to the channel unit 3, and a function of adding frame check data to the fixed-length first character string of the transmission data from the channel unit 3. This problem can be solved by providing the additional device 4 for check sequence.

〔作用〕[Effect]

本発明に依るとデータ中継に際し、ヘッダ■(の後に在
るFe2Oを受信した段階でフレームチェックシーケン
スを行い、続くデータを受信中に次の発送準備が完了し
ているので中継時間が短縮出来ると云う効果が生まれる
According to the present invention, when relaying data, a frame check sequence is performed at the stage when Fe2O located after the header () is received, and preparation for the next shipment is completed while the following data is being received, so the relay time can be shortened. This effect is produced.

〔実施例〕〔Example〕

第1図は本発明に依る伝送フレームの一実施例を示す図
である。
FIG. 1 is a diagram showing an embodiment of a transmission frame according to the present invention.

従来の伝送フレームでは唯一個のFe2を使用していた
が、本発明では二つのFe2 (Fe2OとFC3L)
を使用する。
In the conventional transmission frame, only one Fe2 was used, but in the present invention, two Fe2 (Fe2O and FC3L) are used.
use.

F、C5OはヘッダHに対するフレームチェックシーケ
ンスを行い、FC3Iは従来方式と同く全フレームに対
するフレームチェックシーケンスを行う。
F and C5O perform a frame check sequence for header H, and FC3I performs a frame check sequence for all frames as in the conventional system.

従って中継局側では、Fe2 Oを受信した段階で直ち
にフレームチェックシーケンスを行い、宛先、発信元を
確認することが出来る。従ってFe2Oを受信してフレ
ームチェックシーケンスを終わった時点−伝送りを受信
している時点−次の受信局に対する発送準備を行ってデ
ータDの受信、Fe21によるフレームチェックシーケ
ンスを終了すると直ちに発送可能となり、中継時間を短
縮する、−とが出来る。
Therefore, on the relay station side, upon receiving Fe2O, it can immediately perform a frame check sequence and confirm the destination and source. Therefore, when Fe2O is received and the frame check sequence is finished - when the transmission is being received - preparations for sending to the next receiving station are made, data D is received, and as soon as the frame check sequence by Fe21 is finished, sending is possible. , shorten relay time, -.

第2図は本発明に依る通信制御装置の機器構成を示す。FIG. 2 shows the equipment configuration of a communication control device according to the present invention.

第3図は本発明に依るFe2−ADPの一構成例を示す
FIG. 3 shows an example of the configuration of Fe2-ADP according to the present invention.

図中、1はプロセッサ(CPU) 、2はメモリ(ME
M) 、3はダイレクトメモリアクセス制御部/データ
チャンネル(DMAC/DCH) 、4はフレームチェ
ックシーケンス用付加装置(Fe2−ADP)、56〜
5Nは夫々回線性0〜#N用の文字組立/分解部(UR
T) 、4.は演算部(ALU) 、4□はラインメモ
リ (LM)、43は対チヤンネル制御部、44は対U
RT制御部である。
In the figure, 1 is the processor (CPU), 2 is the memory (ME
M), 3 is a direct memory access control unit/data channel (DMAC/DCH), 4 is an additional device for frame check sequence (Fe2-ADP), 56-
5N is a character assembly/disassembly unit (UR
T), 4. is the arithmetic unit (ALU), 4□ is the line memory (LM), 43 is the channel control unit, and 44 is the pair U
This is an RT control section.

第2図に示す様に本発明に依る通信制御装置は回線毎に
文字組立/分解部を持っている。即ち、回線#0用の文
字組立/分解部URT50、回線#N用の文字組立/分
解部URT5N等が設けられている。
As shown in FIG. 2, the communication control device according to the present invention has a character assembly/disassembly section for each line. That is, a character assembly/disassembly section URT50 for line #0, a character assembly/disassembly section URT5N for line #N, etc. are provided.

DMAC/DCH3とURT50〜U RT 5 Nの
間にFe2−ADP4を設ける 本発明に依るFe2−ADP4はデータ送信開始と同時
に内蔵するバイトカウンタをリセットして計数を開始し
、一定バイト数になるとFe2 Oを付加し、指定され
た回線#NのURT511へ転送する。
Fe2-ADP4 is provided between DMAC/DCH3 and URT50 to URT5N. Fe2-ADP4 according to the present invention resets the built-in byte counter and starts counting at the same time as data transmission starts, and when a certain number of bytes is reached, Fe2 0 is added and transferred to the URT 511 of the designated line #N.

Fe2−ADP4は第1図に示すデータDを送出し終わ
るとURT5Nに対しデータDの送信終了を指示する。
When Fe2-ADP4 finishes sending data D shown in FIG. 1, it instructs URT5N to finish sending data D.

U RT 5 Nは此の指示を受けてFCSIを付加し
て回線#Nへ送出する。
Upon receiving this instruction, U RT 5 N adds FCSI and sends it to line #N.

Fe2−ADP4は回線#NのURT5Nからのデータ
受信開始と同時に内蔵するバイトカウンタをリセットし
て計数を開始し、一定バイト数になると(Fe12分)
、Fe2Oによるフレームチェックシーケンスを行い、
ヘッダHの正常性を確認する。若し異常があればDMA
C/DCH3へ此れを通知する。
Fe2-ADP4 resets its built-in byte counter and starts counting at the same time as it starts receiving data from URT5N of line #N, and when it reaches a certain number of bytes (Fe12 minutes)
, performs a frame check sequence using Fe2O,
Check the normality of header H. DMA if there is any abnormality
Notify this to C/DCH3.

更に後続データを受信すると、URT5Nはフレーム全
体のチェック結果をFe2−ADP4へ通知する。Fe
2−ADP4は此の通知をDMAC/DCH3へ通知し
、DMAC/DCH3は更にプロセッサ1へ通知する。
Upon receiving further data, the URT5N notifies the Fe2-ADP4 of the check result for the entire frame. Fe
2-ADP4 notifies this notification to DMAC/DCH3, and DMAC/DCH3 further notifies processor 1.

本発明に依るFe2−ADP4の機器構成は、第3図に
示す通りで、A L U 4 +はフレームチェックシ
ーケンスの演算を行う所であり、LM4□はA L U
 4 I に対するワーキングメモリの役目をするライ
ンメモリで回線別に割宛てられたメモリエリアを持ち、
ALU41が時分割動作が行える様になっている。
The equipment configuration of Fe2-ADP4 according to the present invention is as shown in FIG.
4 The line memory serves as working memory for I, and has a memory area allocated to each line.
The ALU 41 is capable of time-division operation.

対チヤンネル制御部43はDMAC/DCH3に対する
インタフェイスの役目を果たし、対URT ?t+制御
部44はU RTに対するインクフェイスとして動作す
る。
The channel control unit 43 serves as an interface for the DMAC/DCH3, and controls the URT? The t+ control section 44 operates as an ink face for the URT.

尚第2図の例では、Fe2−ADP4に於いてFe2O
を付加する方法を採っているが、Fe2−ADP4をD
MAC/DCH3に機能を併合さDMAC/DCH3で
発生させる方法も同様に可能である。
In the example of Fig. 2, Fe2O in Fe2-ADP4
However, Fe2-ADP4 is
It is also possible to merge functions into MAC/DCH3 and generate them in DMAC/DCH3.

〔発明の効果〕〔Effect of the invention〕

以上詳細に説明した様に本発明によれば、データの中継
時間が短縮出来ると云う大きい効果がある。
As described above in detail, the present invention has the great effect of shortening the data relay time.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明に依る伝送フレームの一実施例を示す図
である。 第2図は本発明に依る通信制御装置の機器構成を示す。 第3図は本発明に依るFe2−ADPの一構成例を示す
。 第4図は従来の伝送フレームの一例を示す。 図中、Fはフラグ、Hはヘッダ、Dはデータ、Fe2.
Fe2O2及びFCSIは夫々フレームチェックシーケ
ンス、1はプロセッサ、2はメモリ、3はDMAC/D
CH,4はFe2−ADP。 50〜5Nは夫々文字組立/分解部(URT)、4、は
演算部、4□はラインメモリ、43は対チヤンネル制御
部、44は対URT制御部である。 i々♀トソ耳(二よ4仏?茫−)し−乙の−¥::Xn
J早 1 図 令完■月(ギるj表引きキj偵アぞ弓!のネ喋1仁〕l
\矛 2 圀 ホ介朗14るfcs−ADP/)−講べ例茅 、3 図 徒氷の七及迭フし−、乙、め−!l 事 4 図
FIG. 1 is a diagram showing an embodiment of a transmission frame according to the present invention. FIG. 2 shows the equipment configuration of a communication control device according to the present invention. FIG. 3 shows an example of the configuration of Fe2-ADP according to the present invention. FIG. 4 shows an example of a conventional transmission frame. In the figure, F is a flag, H is a header, D is data, Fe2.
Fe2O2 and FCSI are frame check sequences respectively, 1 is processor, 2 is memory, 3 is DMAC/D
CH,4 is Fe2-ADP. 50 to 5N are character assembling/disassembling units (URT), 4 is an arithmetic unit, 4□ is a line memory, 43 is a channel control unit, and 44 is a URT control unit. i♀Toso ears (two and four Buddhas? 茫-)shi-Otsu-no-¥::Xn
J-early 1 Zurei complete ■ month
\Spring 2 Hosukero Kuni 14ru fcs-ADP/) - Lecture Example Kaya , 3 Figures are the seventh of the ice, Otsu, Me -! l Matter 4 Figure

Claims (1)

【特許請求の範囲】 フレームチェックシーケンス方式を採る通信制御装置に
於いて、 回線毎の文字組立/分解部(5_0〜5_N)、該文字
組立/分解部(5_0〜5_N)に於いて組立られた受
信文字と分解されて送信される文字をメモリ(2)の間
で転送制御するチャンネル部(3)、及び該文字組立/
分解部(5_0〜5_N)と該チャンネル部(3)の間
にあって固定長の最初の文字列のフレームチェックを行
って該チャンネル部(3)に報告する機能と該チャンネ
ル部(3)からの送信データの固定長の最初の文字列に
フレームチェックデータを付加する機能を有するフレー
ムチェックシーケンス用付加装置(4)を具備すること
を特徴とするフレームチェックシーケンス方式。
[Claims] In a communication control device that adopts a frame check sequence method, a character assembly/disassembly unit (5_0 to 5_N) for each line, and a character assembly/disassembly unit (5_0 to 5_N) that a channel unit (3) for controlling the transfer of received characters and characters to be disassembled and transmitted between the memory (2);
A function located between the decomposition unit (5_0 to 5_N) and the channel unit (3) to check the frame of the first character string of a fixed length and report it to the channel unit (3), and transmission from the channel unit (3). A frame check sequence method characterized by comprising a frame check sequence adding device (4) having a function of adding frame check data to a first character string of a fixed length of data.
JP60196388A 1985-09-05 1985-09-05 Frame check sequence system Pending JPS6257345A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60196388A JPS6257345A (en) 1985-09-05 1985-09-05 Frame check sequence system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60196388A JPS6257345A (en) 1985-09-05 1985-09-05 Frame check sequence system

Publications (1)

Publication Number Publication Date
JPS6257345A true JPS6257345A (en) 1987-03-13

Family

ID=16357040

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60196388A Pending JPS6257345A (en) 1985-09-05 1985-09-05 Frame check sequence system

Country Status (1)

Country Link
JP (1) JPS6257345A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63292843A (en) * 1987-05-01 1988-11-30 バイタリンク・コミュニケーションズ・コーポレーション Method and apparatus for connecting interface to local area network
US4857895A (en) * 1987-08-31 1989-08-15 Kaprelian Edward K Combined scatter and light obscuration smoke detector
WO1999007100A1 (en) * 1997-08-01 1999-02-11 Ntt Mobile Communications Network Inc. Data sequence generator, transmitter, information data decoder, receiver, transceiver, data sequence generating method, information data decoding method, and recording medium

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63292843A (en) * 1987-05-01 1988-11-30 バイタリンク・コミュニケーションズ・コーポレーション Method and apparatus for connecting interface to local area network
US4857895A (en) * 1987-08-31 1989-08-15 Kaprelian Edward K Combined scatter and light obscuration smoke detector
WO1999007100A1 (en) * 1997-08-01 1999-02-11 Ntt Mobile Communications Network Inc. Data sequence generator, transmitter, information data decoder, receiver, transceiver, data sequence generating method, information data decoding method, and recording medium
US6522665B1 (en) 1997-08-01 2003-02-18 Ntt Docomo, Inc. Data sequence generator, transmitter, information data decoder, receiver, transmitter-receiver, data sequence generating method, information data decoding method, and recording medium

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