JPS6254943A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To eliminate disconnection of wirings by forming the stepwise shape of wirings of a lower layer in a semiconductor device having multilayer interconnections in a smooth slope. CONSTITUTION:Wirings 2b of lower layer is formed of the same as or different material from the material of wirings 2a of the first layer on an Si substrate 1, and with a photoresist 3a coated then as a mask the wirings 2b are etched. When the photoresist 3a is removed to form the wirings 2a, the corner of the wirings 2a on the corner of the step of the wirings 2b is formed with a step having a smooth slope. Thereafter, a photoresist 3b is coated, a wiring pattern is transferred so that the corner formed with a smooth slope of the wirings 2a coincides with the edge of the photoresist 3b. Then, the wirings 2a is etched, the photoresist 3b is removed to from smooth slope of the step of the wirings 2a. When an interlayer interconnection film 4 is then formed, the step coating property is improved. Then, the wirings 5 of the second layer is formed.

Description

[Detailed Description of the Invention] [Industrial Application] The present invention provides a semiconductor device with improved step coverage of an interlayer insulating film, upper layer wiring, and a protective film when manufacturing a semiconductor device having multilayer wiring. The present invention relates to a manufacturing method.

[Conventional technology]

FIGS. 2(IL) to 2(e) are cross-sectional views showing a conventional method of manufacturing a semiconductor device having multilayer wiring. In these figures, 1 is the Si substrate that has been completed with element formation and wiring connection hole formation immediately before wiring, 2a is the first layer of wiring, 3a is the photoresist interlayer insulating film, and 5 is the upper second layer. It's the wiring.

Next, the manufacturing method will be explained. As shown in FIG. 2(a), a first layer of wiring 2a is formed on the Si substrate 1. Thereafter, a photoresist 3a is applied, masked, exposed, developed, and a wiring pattern is transferred by photolithography. Next, as shown in FIG. 2(b), the first layer wiring 2a is anisotropically etched using the seventh resist 3a as a mask. Thereafter, when the photoresist 3a is removed, a -M-th grid t12a is formed as shown in FIG. 2(e). Next, Figure 2 (d
), an interlayer insulating film 4 is formed. Next, Figure 2 (
As in e), after forming the interlayer communication holes, the second layer wiring 5 is formed.

[Problem that the invention seeks to solve]

- In the conventional manufacturing method of a semiconductor device, when forming the interlayer insulating film 4, the second layer wiring 5, and a film thereon as described above, the -i-th wiring 2a is formed by anisotropic etching. In this case, since there is a vertical step, there are problems such as poor step coverage (step coverage/edge) and the second layer wiring 5 breaking at the step.

The present invention was made to solve the above-mentioned problems, and an object of the present invention is to provide a method for manufacturing a semiconductor device that improves step coverage.

[Means for solving problems]

In the method for manufacturing a semiconductor device according to the present invention, a lower layer wiring having a step with a gently sloped end is formed on a semiconductor substrate, a first layer wiring is formed on the lower layer wiring, and then the -Im An interlayer insulating film is formed on the entire surface including the second wiring, and then wiring and an interlayer insulating film are sequentially formed on this interlayer insulating film.

[Effect]

In this invention, the step coverage of the interlayer insulating film is improved by making the slope of the step portion of the lower layer wiring pattern formed before the formation of the first layer wiring more gentle, and the step coverage of the interlayer insulating film is improved. The step coverage of the wiring is also improved and there is no disconnection.Furthermore, the step coverage of the film on the second layer wiring is also improved.

〔Example〕

FIGS. 1(a) to (i) are cross-sectional views showing a manufacturing method according to an embodiment of the present invention, in which the same reference numerals as in FIGS. 2(a) to (e) indicate the same parts, and 2b indicates the first layer. 3 is a photoresist layer formed to soften the edges of the step of the wiring 2a.Next, a method for manufacturing a semiconductor device according to the present invention will be described. As shown in FIG. 1(a), a lower layer wiring 2b is formed on an 81 substrate 1 using a material that is the same as or different from that of the first layer wiring 2a. Then photoresist is transferred. Next, as shown in FIG. 1(b), the underlying interconnection 2b is etched by isotropic etching using the photo-cyst 3a as a mask. Next, as shown in FIG. 1(e), after photoresist is applied, a first layer of wiring 2a is formed as shown in FIG. 1(d). At this time, the corner of the first layer wiring 2a above the corner of the step of the lower layer wiring 2b becomes a step with a gentle slope. Thereafter, as shown in FIG. 1(e), a photoresist wiring pattern is further transferred. At this time, the first layer wiring 2n
The edge of the cyst 3b is aligned with the gently sloped corner of the cyst 3b.

Next, as shown in FIG. 1(f), the first layer wiring 2a is etched by anisotropic etching. Next, as shown in FIG. 1(g), the edges of the step of the first layer wiring 2a are made to have a gentle slope by applying photoresist. Next, as shown in FIG. 1(h), the interlayer insulating film 4
When formed, the step coverage of the first layer wiring 2a is improved because the edges of the steps are gently sloped. Next, as shown in FIG. 1(1), a second layer of wiring 5 is formed.

At this time, step coverage is similarly improved and wire breakage is eliminated.

Note that in the above embodiment, the first and second layer wirings 2a, 5
However, in multilayer wiring, the n-th layer and ( n +1.
) Layer wiring can also be manufactured by stacking them in the same way.

Furthermore, the Si substrate 1 is not limited to Si, and may be any other semiconductor substrate.

〔Effect of the invention〕

As explained above, the present invention forms a lower layer wiring having a gently sloped step on a semiconductor substrate,
A first layer of wiring is formed on this lower layer of wiring, then an interlayer insulating film is formed on the entire surface including the first layer of wiring, and further wiring and an interlayer insulating film are sequentially formed on this interlayer insulating film. Therefore, in a semiconductor device with multilayer wiring, the step shape of the lower wiring is formed with a gentle slope.
This has advantages such as improved step coverage of the interlayer insulating film, improved step coverage of the upper layer wiring, and elimination of disconnections.

[Brief explanation of the drawing]

FIGS. 1(a) to (i) are cross-sectional views showing one embodiment of the present invention, and FIGS. 2(a) to (e) are cross-sectional views showing a conventional method for forming multilayer wiring. In the figure, 1 is a Si substrate, 2a is the first layer wiring, 2b
3a and 3b are photoresist layers 15, 4 are interlayer insulating films, and 5 is a second layer wiring. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masuo Oiwa (2 others) Figure 1 Figure 1 Figure 2

Claims (1)

[Claims] In a semiconductor device having multilayer wiring, a lower layer wiring having a step with a gently sloped end is formed on the semiconductor substrate, a first layer wiring is formed on this lower layer wiring, and then the first layer wiring is formed. 1. A method of manufacturing a semiconductor device, comprising: forming an interlayer insulating film on the entire surface including the interlayer insulating film, and sequentially forming wiring and an interlayer insulating film on the interlayer insulating film.