JPS6249476A - Memory access control system - Google Patents

Abstract

PURPOSE:To simplify a picture information processing at the time of multiple gradation and polychromic display and to improve picture quality by providing a processing section provided with a means to access a storage section having the area of specified quantity as an access unit and a setting section having a means that sets address information that designates each area of specified quantity one by one in a register. CONSTITUTION:In case where a processing device 5 reads picture information in plane memories F1-F3, a setting section 10 sets the address r1 of a byte area in which the picture information R1 of a plane memory F1 is included to a head digit C1, and sets the address g1 of a byte area in which the picture information G1 of the plane memory F2 is included to the next digit C2. Further, the section 10 sets the address b1 of a byte area in which picture information B1 of the plane memory F3 is included to the next digit C3, and makes address setting so as to allow successive and simultaneous access. When a processing section 6 reads data, access is made successively in parallel one by one in the unit of byte or word or simultaneously. Accordingly, the shift of color etc. is not caused in the graphic form.

Description

[Detailed Description of the Invention] [Summary] In an image processing system in which image M4 information indicating attributes such as color type and gradation of a displayed image is stored in a plurality of memories, a processing device accesses the plurality of image memories. At this time, data located at the same address in each image memory is simultaneously accessed and updated.

[Industrial application field]

The present invention relates to an improvement in a memory access control method in which a processing device accesses a plurality of memories storing image information.

It is desired to simplify access processing when a processing device reads or writes image information in an image memory.

[Conventional technology]

A conventional example will be explained using figures. FIG. 3 is a block diagram illustrating a conventional example.

In the conventional example, image information for each color is stored in three plane memories F1 to F3. That is, on the screen 2 of the display unit (CRT display unit) 1, three color image information (R+ ~R,,), (at ~G,,) for displaying the diagonal line figure 3 in color are displayed.
and (B, ~B, ,) are respectively plane memories F,
~F, is stored. Note that the image information is that of a dot image, (R, ~R,) is red image information, (G1
~GLl) is green image information, and (B+ ~B,,)
is blue image information t. These brain memories F, ~
The image information of R1 is sent from the display control section 4 to the display section 1, and the diagonal line figure 3 is displayed in color on the screen 2. In other words, the three primary colors (red,
The diagonal line figure 3 is displayed in color based on the image information (green and blue). Note that the plain memories F1 to F by the processing device 5
Access to 3 is performed for each byte (or word) unit area (this is called a byte area). For example, image information R0
Assuming that the address r1 of the byte-built HI area containing the byte area is designated as r1, the image information in the byte area is updated by specifying this address.

In the graphic display system as described above, when the processing device 5 accesses the plane memories F1 to F, conventionally a method has been adopted in which each brain memory is sequentially accessed. That is, prior to access, the processing unit 6 stores the following information in the register 7.
First, after setting the addresses r, ~r7 of the image quality NR, ~R, of the plane memory F, the address of the register 7 (
r+ to rn) Based on the information, each address in the plane memory 1 is sequentially accessed to update the image information, etc.

Next, the processing unit 6 sets the addresses g, ~gn of the image information G, ~Gl, of the plane memory F2 in the register 7, and then accesses the plane memory F2 in the same manner as described above to update the image information, etc. conduct. Image information within a brain memory unit is also accessed using the same procedure as above.

As described above, conventionally, the processing device 5 accesses the plane memories F, -F3 sequentially in units of brain memories.

[Problem that the invention seeks to solve]

As is clear from the above, in graphic display systems having a plurality of plane memories, when a processing device accesses the plane memories, a method has been adopted in which the plane memories are sequentially accessed in units of brain memories. For this reason, when updating image information, etc., the image information in some brain memories has been updated, but the image information in other plane memories has not been updated, resulting in color shifts and disturbances in tone on the display screen. There was a problem in that it caused problems such as

[Means for solving problems]

FIG. 1 is a block diagram of the principle of the present invention. The present invention provides a system for displaying figures, etc. in multiple colors by sending dot image information stored in the storage unit 11 to the display unit 1, which includes: accessing the storage unit 11 using a predetermined amount of area as an access unit; a register 7 in which the address of a predetermined amount of area is set; and a means for setting address information 12 for specifying each predetermined amount of area in the plurality of storage units 11 in the register 7. The processing device 5 includes a setting section 11 .

[Effect]

When the processing device 5 retrieves or updates data in the storage unit 11, the processing unit 6 extracts one data for each predetermined amount of area in the plurality of storage units 11 based on the address information 12 set in the register 7. access one by one, sequentially or simultaneously.

〔Example〕

Hereinafter, the present invention will be explained with reference to the drawings. FIG. 2 is a block diagram illustrating an embodiment of the present invention.

Image information of the diagonal line figure 3 displayed in color on the screen 2 of the display unit 1, that is, red image information n (R1-Rn), green image information (G+ ~Gn), and blue image information (B, ~Bn) but,
They are stored in plane memories F, , F2 and F3, respectively. By sending these three primary color information to the display section 1 by the display control section 4, the diagonal line figure 3 is displayed in color. Note that writing of image information into the plane memories F1 to F is performed by a write control section 8, and reading of image information from the plane memories F, to F is performed by a succession control section 9.

Plain memories F, ~F3 are dot image memories, and when accessing image information in the plain memory, for example R, the image information is accessed based on the address r of the byte area (indicated by a broken line) containing the image information R1. to access. In the embodiment, access is performed in byte (8 bit) units, but this may also be in word (WORD) units.

For example, the processing device 5 stores image information (R, ~Rn), (01~Gn), and (B + ~B) in the brain memories F1~F3.
n), the setting unit 10 sets address information in the register 7 as shown in the figure. The first (rightmost) digit C7 of register 7 contains image information R1 of plain memory F.
The next digit C2 is set to the address g1 of the byte area containing the image information G of the plain memory F2, and the next digit C1 is set to the address r of the byte area containing the image information G of the plain memory F2. The address b of the byte area containing the image information B of F is set.

Similarly, in the digits after digit C4 of register 7, the address r Z+ gz+ b2+ r :++ gi+ b3
The addresses are set so that the image information in the brain memories F, ~F, can be accessed one byte at a time, sequentially or simultaneously.

After this address setting is performed, the processing unit 6 reads data in the BY1- area containing the image information R1 of the plain memory F+ based on the address r1 of the first digit C1 of the register 7. Similarly, the address g of the next digit C2
Based on +, the data including the image information G in the plane memory F2 is read out. In other words, data reading by the processing unit l is performed using the plain memory F++
F! +F 3 sequentially or simultaneously, one byte at a time. On the other hand, in the case of data writing, the access order is exactly the same.

As described above, when accessing data in a plurality of memory planes, the present invention sequentially or simultaneously accesses the image information in each plane one byte or word at a time in parallel, thereby causing color misalignment in figures. etc. will not occur.

Note that the image information, for example, R+, G++B+, is image information related to the same dots that make up the three diagonal lines.
The same applies to other Rz, Gz, Bz, etc.

Further, in the embodiment, image information for each color is stored in the plain memories F1 to F3, but these may be image information related to color tone.

〔Effect of the invention〕

In color graphic display, the present invention has the advantage of simplifying image information processing in multi-gradation and multi-color display, and also improving image quality.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the principle of the present invention. FIG. 2 is a block diagram explaining an embodiment of the present invention. FIG. 3 is a block diagram explaining a conventional example. Diagonal line figure, 4 is a display control section, 5 is a processing device, 6 is a processing section, 7 is a register, 8 is a write control section, 9 is a continuation control section, 10 is a setting section, 11 is a storage section, 12 address information show.

Claims (1)

[Claims] It has a processing device 5, a plurality of storage units 11, and a display unit 1,
In a system that sends dot image information stored in a storage unit 11 to a display unit 1 to display figures, etc., the processing unit 6 has means for accessing the storage unit 11 using a predetermined amount of area as an access unit; and a predetermined amount of area. The processing device 5 is provided with a register 7 in which an address is set, and a setting unit 10 having means for setting in the register 7 address information 12 that specifies each predetermined amount of area in the plurality of storage units 11 one by one. When the device 5 retrieves or updates data in the storage unit 11, the processing unit 6 extracts one data for each predetermined amount of area in the plurality of storage units 11 based on the address information 12 set in the register 7. A memory access control method characterized by sequential or simultaneous access.