JPS6246035B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a pattern separation and identification processing method, in particular, a direct contact linear component of a wiring pattern that is in direct contact with a block pattern.
Assign one label and then assign the same label to the linear components connected to it.
The present invention relates to a pattern separation and identification processing method that assigns the same label to wiring patterns that are to be electrically connected to each other.

When designing logic circuit diagrams, etc., figures are drawn by hand based on predetermined drawing rules, and then various line segments on this handwritten drawing are designed and drawn.
Automation systems are being adopted that convert codes into codes that match the automation system and automatically manufacture circuit patterns based on this code.

In order to solve the above-mentioned problems, the present invention provides, for example, a first
From the logic circuit original diagram as shown in the figure, extract each straight line component, . The purpose is to integrate the labels of linear components of wiring patterns to be electrically connected to each other as shown in FIG. 4. That is, the present invention ignores the logic circuit blocks 1-1 to 1-15 shown in FIG.
As shown in the figure, the coordinates (x _s , y _s ) (x
_e , y _e ) and the connection code described later, and then give a common label to a single wiring pattern as shown in the straight line component shown in Figure 3, . . . It is characterized in that the same label is given to the same wiring pattern based on the electrical connection points, as shown in FIG. This will be explained below with reference to the drawings.

Figure 1 shows the original figure to be processed by the present invention;
The figure is an explanatory diagram showing a state in which straight line components belonging to a wiring pattern are extracted from the original figure shown in Figure 1, FIG. FIG. 5 and FIG. 6 are explanatory diagrams explaining an example of the drawing rules according to the present invention. FIG. 7 is an overall configuration diagram of an embodiment of the present invention. FIG. 8 is an explanatory diagram for explaining the connection code according to the present invention, FIG. 9 is an example of the processing result by the direct contact linear component extraction processing unit 6 shown in FIG. 7, and FIG. 10 is a wiring pattern label shown in FIG. 7. 11 is an explanatory diagram showing the processing of the conversion processing section 7 and the label correction processing section 8 in the form of a flowchart. FIG. 11 is an example of the wiring pattern label processing section 7 shown in FIG. 7. FIG. 10 is an embodiment of the circuit corresponding to the vertical direction processing in the process [ ] shown in FIG. 10, and FIG.
Figures 4 to 20 show the processing modes when performing the processes [], [], [] shown in Figure 10,
FIG. 21 is an explanatory diagram showing unintegrated labels and their processing modes, FIG. 22 is a flowchart showing an embodiment of the label integration processing section 9 shown in FIG. 7, and FIG. is the process shown in Figure 22 []
FIGS. 24 and 25 are explanatory diagrams illustrating the processing mode of the label integration processing section 9 shown in FIG. 7, according to one embodiment.

Assume that the above handwritten drawing is drawn as a pattern 4 on a predetermined mesh 3 as shown in FIG. 5, and that the following rules exist for drawing the pattern 4. explain.

That is, (A) On the mesh 3, there are break positions such as the predetermined X coordinates XH ₁ to XH ₅ , and the logic circuit pattern block (block pattern) 1
The left side of always has one of the above X coordinates XH ₁ , XH _{2 .} . . . Therefore, as shown in FIG. 6A, there is no block 1 whose left side does not have an X coordinate, such as _XH1 .

(B) Wiring pattern 2 drawn on mesh 3 is drawn along the line segment on mesh 3.
It extends only to the bottom, left, or right. Therefore, a wiring pattern such as that shown in FIG. 6B does not exist.

(C) The right side of the block pattern 1 drawn on the mesh 3 may or may not have the above-mentioned X coordinates XH ₁ , XH ₂ , etc., and generally does not match the coordinates.

(D) Input side wiring pattern 2 for block pattern 1 drawn on mesh 3
is input to block pattern 1 only from the left side of block pattern 1, and output side wiring pattern 2 is output from only the right side of block pattern 1. Therefore, the pattern shown in the upper part of FIG. 6C does not exist.

(E) I/O wiring pattern 2 touches block pattern 1 at an intermediate position on the left or right side. Therefore, the pattern shown in the lower part of FIG. 6C does not exist.

(F) Electrical connection points for wiring pattern 2 are always T-branched, and + branching points on the figure are electrically non-contact points.

FIG. 7 shows an overall configuration diagram of an embodiment of the present invention,
Reference numeral 5 in the figure is a vector figure that is divided into each existing linear component as shown in Figure 2 (generally, the coordinates of the starting end point and the coordinate of the ending point of each linear component and the coordinates of each end point will be described later). (concatenated codes are summarized in a table). Reference numeral 6 represents a direct contact linear component extraction processing unit, which performs processing to extract the linear component of the wiring pattern that is in direct contact with the logic circuit block pattern described above (this processing is described in the "Graphic (disclosed in ``Pattern Separation and Extraction Processing Method''). Information on the processing results will be described later using FIG. 9. 7 is the wiring
a pattern labeling processing unit, a tenth;
As will be described later with reference to FIGS. 11 and 12, a process is performed to label each straight line component that clearly belongs to the wiring pattern. 8 is
The label correction processing section performs a process of correcting and unifying the labels given by the processing section 7, as will be described later with reference to FIGS. 10 and 13. 9 is a label integration processing section;
As will be described later with reference to FIGS. 1, 22, and 23, a process is performed to integrate wiring patterns that should originally be electrically connected to each other so as to give the same label.

Prior to the description of the present invention, the connection code referred to in the present invention will be explained with reference to FIG. In the case of the present invention, as shown in FIG. 8A, assuming that there is an end point T of a straight line component, a concept called a "connection code" is introduced to describe in which direction the straight line component extends from the end point T. ing. And the eighth
As shown in Figure B, if it extends horizontally to the right, a logic "1" is given to the direction code "1",
When extending vertically upward, logic "1" is given to direction code "2"; when extending horizontally to the left, logic "1" is given to direction code "3"; When extending vertically downward, a logic "1" is given to the direction code "4".

FIG. 9 shows an example of a processing result by the direct contact linear component extraction processing section 6 shown in FIG.

Now suppose that vector figure 5 corresponds to FIG. 9A, and logic circuit block pattern 1
Suppose that straight line components of wiring pattern 2 that are in direct contact with are extracted as shown by thick lines, . . . . In this case, the vector figures 5 described in the form of a table are associated as shown in FIG. 9B. Note that the "line segment" in Figure 9B
,,...correspond to the straight line component (direct contact straight line component) in Figure 9A, "Start ADD" corresponds to the coordinates of the starting point of the said straight line component, and the "connection code" that follows it corresponds to the coordinates of the starting end point of the said straight line component. Represents the concatenation code. Further, "end ADD" corresponds to the coordinates of the terminal point of the linear component, and "connection code" following it represents the connection code of the terminal point. Furthermore, the "left side" in the figure is the left side code, and when the logic is "1", it means that the linear component is in contact with the left side of the logic circuit block 1, and the "right side" is the right side code, which is the logic "1". '' means that the linear component is in contact with the right side of the logic circuit block 1.

For example, regarding a straight line component, the starting point (x ₁ , y ₁ ) of the component is given the connection code "1011" because there is no straight line component in the vertically upward direction, and the ending point (x ₁ ′, y ₁ ′ ) is given the concatenation code "0111" because there is no component in the horizontal left direction, and because it is in contact with the left side of logic circuit block pattern 1, the left side code is given logic "1".

Hereinafter, in this specification, it is assumed that the results shown in FIG. 9 have already been obtained, and the subsequent steps will be specifically explained.

FIG. 10 is an explanatory diagram showing the processing of the wiring pattern labeling processing unit 7 and label correction processing unit 8 shown in FIG. ] stage and processing [ ] stage and processing [ ] stage.

As shown in FIG. 9B, the process [] gives a certain label to the straight line component directly in contact with the left side of the logic circuit block pattern 1, and gives labels to other straight line components connected to the straight line component. I will do it.
Then, modify the label.

Next, the process [] is performed on the vector figure 5 shown in FIG. 0010”
or "0001" (not shown in Figure 9B - for example, the straight line component with the end point shown in Figure 2), give a certain code to the component, and Labels are given to other linear components connected to the component. Furthermore, as shown in FIG. 9B, the logic circuit block
A certain label is given to a straight line component directly in contact with the right side of pattern 1, and labels are given to other straight line components connected to this straight line component. Then, correct the label.

Next, the straight line components that were not labeled due to the T-branch are labeled.

FIG. 11 shows an embodiment of the wiring pattern labeling processing section 7 shown in FIG.

Now, the vector figure 5 as shown in FIG.
Assume that it is as shown in Figure A or B. In this case, as can be seen from the vector diagram 5, the straight line component , , is in direct contact with the left side of the logic circuit block pattern 1 (left side code logic "1"). Regarding this vector figure 5, a straight line component whose left-hand side code has logic "1" is extracted as shown in FIG. 11C (descriptions of blank spaces in FIG. 11C are omitted). For the straight line component extracted at this time, as shown in Fig. 11C,
Labels are given in order as "1", "2", and "3".

Then, by the vertical direction processing and horizontal direction processing shown in Figure 10, the illustrated process [ ], extracts other straight line components that are vertically connected to the labeled component and gives them the same label. Then extract other line components connected horizontally to that line component and give them the same label, and then extract other line components connected vertically to that line component. and give the same label, and... The processing during this period stops when it reaches a component that has already been labeled or a T-branch.

Regarding the linear components shown in FIG. 11, in the first vertical processing, as shown in FIG. A label "3" is assigned to the item.
Then, in the next horizontal direction process, FIG.
As shown, the label "2" is given to the component.

FIG. 12 shows an example circuit corresponding to the vertical processing in the process shown in FIG. 10 [ ].
In the figure, numerals 10 and 11 are NAND circuits, 12 to 21 are AND circuits, 22 and 23 are OR circuits, and 24 is a labeling section, for example, the 11th
In the vector graphic 5 shown in FIG. C, a desired label L is written in the "Label" column. In the figure, "i connection code" is the start point connection code of the straight line component to be processed, "i' connection code" is the end point connection code, x _i , y _i are the start point coordinates, x _{i ′} , y _i ′ is also the terminal point coordinate,
Label L is the label of the labeled straight line component to which the target straight line component is connected, x _L , y _L are the coordinates of the starting end point of the labeled straight line component, x _L ′,
Similarly, y _L ' represents the coordinates of the end point. Although the explanation will be omitted, the illustrated signal a indicates that the end point of the quadrant line component to be processed is not a T-junction, and the illustrated signal b
indicates that the linear component to be processed is perpendicular to the labeled linear component, and the illustrated signal C indicates that the labeled linear component has been labeled. And the AND circuit 21
Based on the fact that is turned on, the same label L as the label of the labeled straight line component is given to the straight line component to be processed. Note that for horizontal processing, the same circuit configuration can be used by simply exchanging the input coordinates x and y, and the same applies to vertical processing and horizontal processing in the processing shown in Figure 10 [ ]. It is.

FIG. 13 shows the label correction processing unit 8 shown in FIG.
An example is shown below. It is assumed that the vector figure 5 resulting from the processing up to the labeling processing section 8 shown in FIG. 7 is as shown in FIG. 13A or B. That is, as can be seen from Figure 13A, the label "1" is assigned to the component, the label "2" is assigned to the component, and the label "3" is assigned to the component. Suppose that In this case, the components,,,, are 1
They belong to one wiring pattern and should originally be given the same label. The label correction processing unit 8 shown in FIG. 13 performs this correction process, and extracts straight line components connected to both ends of one straight line component with different labels. In the case shown in the figure, the components are extracted and, for example, the label "2" for the component is modified to the label "3" for the component, and the labels are successively modified thereafter to obtain a vector figure as shown in FIG. 13C.
In the illustrated case, label "2" has been modified to label "3".

Next, it enters the processing section [ ] shown in FIG.
Straight line components of the wiring pattern for which labeling has not been completed at this point in time and whose connection code is "1000", "0100", "0010", or "0001" are extracted and labeled. and,
Vertical processing and horizontal processing are performed in the same manner as above. Next, the linear component of the last label directly in contact with the right side of the logic circuit block pattern is extracted, a label is assigned, and vertical and horizontal processing is performed. Furthermore, the label correction process as described with reference to FIG. 13 above is performed.

After that, the process shown in FIG. 10 is entered, and as can be seen from the circuit diagram in FIG. 12, if there is a T branch, the labeling process is stopped.
Labeling processing may not be performed on straight line components that exist between a branch and another T-branch. Therefore, new labels are assigned to such linear components.

FIGS. 14 to 20 represent processing modes when the processes [ ], [ ], and [ ] shown in FIG. 10 are performed. Note that FIG. 14 shows a stage in process [ ] in which labels "1" to "38" are assigned to linear components directly in contact with the left side of the logic circuit block. FIG. 15 shows a stage in which the first vertical direction processing is performed for the state shown in FIG. 14. FIG. 16 shows the stage immediately before correcting the label in the process shown in FIG. 10,
Labels "13" and "30" conflict. 17th
The figure shows a stage in which the label is corrected for the state shown in FIG. 16. FIG. 18 shows a stage in which the "end points" shown in FIG. 10 are labeled and then subjected to vertical direction processing and horizontal direction processing. FIG. 19 shows a stage in which straight line components directly in contact with the right side of the logic circuit block pattern in the process shown in FIG. 10 are labeled, and then vertical and horizontal processes are performed. Figure 20 is the 10th
The figure shows the stage at which the illustrated process [ ] has been performed.

In the processing up to the label correction processing section 8 shown in FIG. 7, labeling processing and label correction processing as shown in FIGS. 14 to 20 are performed.
However, if this continues, labels that should originally be integrated into other labels will remain unintegrated, as typically seen in the straight line components of the portion sandwiched by T-branches as shown in FIG.

FIGS. 21A and 21B are explanatory diagrams showing such unintegrated labels and their processing modes, respectively,
In the case shown in Figure 21A, the labels "1", "2",
A connected label 〓 is given to the components having "3", "4", "5", etc. as described later, and the same label, for example "6", is given to the component having the connected label. The same applies to the case shown in FIG. 21B.

FIG. 22 is a flowchart showing an embodiment of the label integration processing section 9 shown in FIG. will be carried out. Note that the process [ ] may be considered to be the process corresponding to FIG. 21A, and the process [ ] may be considered to be the process corresponding to FIG. 21B. Processing [ ] performs overall label integration processing.

In the case of process [], first take a T branch (set as T ₁ )
, and set a connected label K to the component. Then, the linear component that is connected to the component and has the same label as the component (the label given by the illustrated label correction processing unit 8 in FIG. 7) is traced, and when the next T branch is detected, the T Let the branch be T ₂ . And between two T branches (T ₁ -
The connection label K set above is set in common for all the components present in T ₂ ). Next, the same connection label K as above is set for the straight line components connected to the T branches _T1 and _T2 . In this state, components connected with T branches may have different connection labels, but the mutual connection labels are unified into one.

In the case of process [], when the above process [] is completed, a component having a T-branch for which no connected label has been set is extracted, and a connected label K is set for one component.

In the process [], if components connected with a T branch have different connection labels, they are integrated into a common connection label.

FIG. 23 shows an embodiment of the process shown in FIG. 22. When the vector figure 5 resulting from the processing up to the label correction processing unit 8 shown in FIG. 7 is shown in FIG. 23A, for example, the thick line components shown in FIG. and〓
and set. Next, as shown in FIG. 23B, for the components connected to the component and the component, respectively,
Set the concatenated label.

Next, paying attention to the T branch point of the components in the case shown, the connected labels 〓 and 〓 are integrated into one as shown in FIG. 23C.

FIG. 24 shows the label integration processing section 9 shown in FIG.
The target portion to be processed is represented by a thick line and an x mark, and FIG. 25 shows the connected label set to the target portion to be processed as shown in FIG. 24.

As explained above, according to the present invention, different labels can be given to each linear component of a wiring pattern to be electrically connected, and a design automation system can be used to It becomes possible to extract valid input information for setting.

[Brief explanation of the drawing]

Figure 1 shows the original figure to be processed by the present invention;
The figure is an explanatory diagram showing a state in which straight line components belonging to a wiring pattern are extracted from the original figure shown in Figure 1, FIG. FIG. 5 and FIG. 6 are explanatory diagrams explaining an example of the drawing rules according to the present invention. FIG. 7 is an overall configuration diagram of an embodiment of the present invention. FIG. 8 is an explanatory diagram for explaining the connection code according to the present invention, FIG. 9 is an example of the processing result by the direct contact linear component extraction processing unit 6 shown in FIG. 7, and FIG. 10 is a wiring pattern label shown in FIG. 7. 11 is an explanatory diagram showing the processing of the conversion processing section 7 and the label correction processing section 8 in the form of a flowchart. FIG. 11 is an example of the wiring pattern label processing section 7 shown in FIG. 7. FIG. 10 is an embodiment of the circuit corresponding to the vertical direction processing in the process [ ] shown in FIG. 10, and FIG.
4 to 20 show the mode of processing when performing the processing shown in FIG. 10 [], [], [],
FIG. 21 is an explanatory diagram showing unintegrated labels and their processing modes, FIG. 22 is a flowchart showing an embodiment of the label integration processing section 9 shown in FIG. 7, and FIG. is the process shown in Figure 22 []
FIGS. 24 and 25 are explanatory diagrams illustrating the processing mode of the label integration processing section 9 shown in FIG. 7, according to one embodiment. In the figure, 1 is a block pattern, 2 is a wiring pattern, 3 is a mesh, 5 is a vector figure, 6 is a direct contact linear component extraction processing section, 7 is a wiring pattern labeling processing section, 8
9 represents a label correction processing section, and 9 represents a label integration processing section.

Claims (1)

[Claims] 1. A block pattern drawn on a predetermined mesh and a wiring pattern that intersects the block pattern are formed by upper, lower, left, and right linear components. The starting point coordinates and end point coordinates of each straight line component on the original figure are extracted from the figure, and based on the extracted original figure linear coordinate information, the block pattern and the wiring pattern existing in the original figure are extracted. A. A direct contact straight line component of a wiring pattern that is in direct contact with the block pattern is extracted, and the start point and/or the end point of the straight line component are extracted as input information to a data processing device. Under the condition where the connected code representing the connected state at the point is extracted,
A wiring pattern in which the same label as the direct contact linear component is given to the linear component of the wiring pattern connected to the direct contact linear component from each extracted direct contact linear component based on the connection code.・Labeling processing unit, B Wiring pattern labeled by the above wiring pattern labeling processing unit
For patterns, patterns in which different labels are given to mutually connected straight line components are extracted, and the same labels are given to the said mutually connected straight line components, and the labels are sequentially changed. A unifying label correction processing unit, for the result corrected by C and the above-mentioned label correction processing unit, converts the result corrected by C and the above-mentioned label correction processing unit into other linear components that are straight line components having a T-branch and connected to both ends of the straight line component. a label integration processing unit that extracts labels that are labeled differently from each other and unifies the labels for the other linear components connected to both ends of the linear component; 1. A pattern separation and identification processing method characterized in that the same label is given to wiring patterns to be connected to each other so that each wiring pattern can be distinguished and extracted from each other.