JPS6245999B2 - - Google Patents
Info
- Publication number
- JPS6245999B2 JPS6245999B2 JP54130464A JP13046479A JPS6245999B2 JP S6245999 B2 JPS6245999 B2 JP S6245999B2 JP 54130464 A JP54130464 A JP 54130464A JP 13046479 A JP13046479 A JP 13046479A JP S6245999 B2 JPS6245999 B2 JP S6245999B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- chip
- heat
- liquid crystal
- conductive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004973 liquid crystal related substance Substances 0.000 claims description 19
- 239000012790 adhesive layer Substances 0.000 claims description 8
- 229920005989 resin Polymers 0.000 claims description 6
- 239000011347 resin Substances 0.000 claims description 6
- 239000012212 insulator Substances 0.000 claims description 5
- 239000010410 layer Substances 0.000 claims description 5
- 239000002245 particle Substances 0.000 claims description 4
- 238000007789 sealing Methods 0.000 claims description 4
- 239000012793 heat-sealing layer Substances 0.000 claims description 3
- 229910003437 indium oxide Inorganic materials 0.000 claims description 2
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 claims description 2
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 claims description 2
- 229910001887 tin oxide Inorganic materials 0.000 claims description 2
- 238000000034 method Methods 0.000 description 9
- 239000004020 conductor Substances 0.000 description 6
- 239000000758 substrate Substances 0.000 description 5
- 238000005476 soldering Methods 0.000 description 4
- 239000004593 Epoxy Substances 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- ISWSIDIOOBJBQZ-UHFFFAOYSA-N Phenol Chemical compound OC1=CC=CC=C1 ISWSIDIOOBJBQZ-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 239000004840 adhesive resin Substances 0.000 description 1
- 229920006223 adhesive resin Polymers 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000012775 heat-sealing material Substances 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 229910052745 lead Inorganic materials 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229920000728 polyester Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
- 238000010618 wire wrap Methods 0.000 description 1
Landscapes
- Liquid Crystal (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Description
【発明の詳細な説明】
本発明はICチツプを搭載し、液晶パネルと接
合されるICチツプ付きの回路基板に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circuit board with an IC chip mounted thereon and connected to a liquid crystal panel.
従来、配線を施した回路基板とIC（集積回路
の略）との接続方法は、現在まで各種考えられて
いる。その１つは、ICをDIP、もしくはフラツ
ト、パツケージに実装し、回路基板上にハンダ付
け、もしくはワイヤラツピングにより、電気装続
する方法、もしくはICチツプそのものを回路基
板上にダイボンドし、ICの各パツドと回路基板
上の端子間をワイヤ、ボンデイングする方法、も
しくはICの各パツド上に金、もしくはSn，Pb等
の低融点金属をバンプ処理して、回路基板上の端
子部へ直接フエースダウンボンデイングする方法
等が考案されている。しかし、上述した方法によ
れば、各端子をハンダ付けする工数、或いはIC
の専有面積の増加、又は１パツド毎のワイヤボン
デイングの工数、金バンプ等の形成コスト等、い
ずれもコストアツプ及び、回路実装面積の増大化
を招いた。 Conventionally, various methods have been considered to connect a circuit board with wiring and an IC (abbreviation for integrated circuit). One method is to mount the IC on a DIP, flat, or package and connect it electrically to the circuit board by soldering or wire wrapping, or to die-bond the IC chip itself onto the circuit board. Either wire or bonding is used between each pad and the terminal on the circuit board, or bump processing with gold or a low melting point metal such as Sn or Pb is performed on each pad of the IC, and the face down directly to the terminal on the circuit board. Bonding methods and the like have been devised. However, according to the method described above, the man-hours for soldering each terminal or the IC
An increase in the area occupied by the circuit board, the number of man-hours required for wire bonding for each pad, and the cost of forming gold bumps, etc., all lead to an increase in costs and an increase in the circuit mounting area.
本発明の目的は電極パツド部に回路基板との接
続を行なう特別のバンプを施す等せず、ICチツ
プをそのまま使用して簡単な方法によりフエース
ダウンボンデイングを行なうことのできるICチ
ツプ付きの回路基板を提供する点にある。 The object of the present invention is to provide a circuit board with an IC chip that allows face-down bonding to be performed by a simple method by using the IC chip as it is without adding special bumps to the electrode pad portion for connection with the circuit board. The point is to provide the following.
次に図面により、本発明の具体的説明を行う。 Next, the present invention will be specifically explained with reference to the drawings.
第１図は、本発明に使用する回路基板の断面図
で、１はガラス、セラミツク等の無機質、もしく
はポリエステル、ポリイミド、フエノール、紙エ
ポキシ、ガラス、エポキシ等の有機質からなる回
路基板、２はカーボン、もしくは銀等の導電粒子
と熱融着樹脂からなる導体配線部、３は上記導体
配線部２上に更に印刷された、やはり導電性粒子
と熱融着樹脂とからなる導電接着層、４，５，６
はそれぞれ熱融着樹脂からなる絶縁体の熱融着層
で導体層と高さを合わせる為、又、ICとの接着
をより確実化させる為、３段印刷処理を施してい
る。上記導体部、絶縁体部は回路基板１上にスク
リーン印刷、もしくはホトエツチング等により、
容易に形成できる。 FIG. 1 is a cross-sectional view of a circuit board used in the present invention, in which 1 is a circuit board made of inorganic material such as glass or ceramic, or organic material such as polyester, polyimide, phenol, paper epoxy, glass, or epoxy; 2 is carbon , or a conductor wiring part made of conductive particles such as silver and a heat-fusion resin; 3 is a conductive adhesive layer further printed on the conductor wiring part 2, also made of conductive particles and a heat-fusion resin; 4; 5,6
In order to match the height with the conductor layer with a thermally adhesive layer of an insulator made of thermally adhesive resin, and to further ensure adhesion with the IC, a three-stage printing process is applied. The conductor portion and insulator portion are formed on the circuit board 1 by screen printing or photoetching.
Easy to form.
第２図は、上記回路基板に直接ICをフエース
ダウンボンデイングを施した断面図で、７はIC
チツプ、８はICチツプ７の電極パツド部であ
る。 Figure 2 is a cross-sectional view of an IC face-down bonded directly to the circuit board, and 7 is an IC.
The chip 8 is an electrode pad portion of the IC chip 7.
本発明においては、シリコーン、ウエハーから
切断されたICチツプを、回路基板上に端子位置
とパツド位置とを顕微鏡等で位置合わせした後、
180℃に加熱されたヘツドをICの裏側から圧力約
４Kg／cm3で約10秒間押しつけることにより、ヒー
トシール材の熱融着樹脂層が融けICチツプを直
接回路基板上に接着し、固定する単位面積当りの
接着力は、導体部、２，３よりも絶縁体部、４，
５，６の方が強く、100ｇ／mm３以上得られる。
通常のICでは、チツプ面積に対するパツド部面
積は約10％と少なく充分実用に耐え得る接着力が
得られる。９はIC７を保護する為のエポキシ等
の樹脂モールド層である。 In the present invention, an IC chip cut from a silicone wafer is aligned with a terminal position and a pad position on a circuit board using a microscope, etc.
By pressing a head heated to 180℃ from the back side of the IC at a pressure of approximately 4 kg/cm 3 for approximately 10 seconds, the heat-sealing resin layer of the heat sealing material melts, directly adhering and fixing the IC chip onto the circuit board. The adhesive strength per unit area is higher for the insulator parts, 4, than for the conductor parts, 2, 3.
5 and 6 are stronger and can obtain more than 100g/ mm3 .
In a typical IC, the pad area is approximately 10% of the chip area, which is small enough to provide enough adhesive strength for practical use. 9 is a resin mold layer such as epoxy for protecting the IC7.
第３図は、本発明の実際の応用例で、上記回路
基板を液晶表示体に応用した例である。１０は液
晶表示体、１１は本発明に基づく回路基板、１２
は液晶表示体１０を表示駆動させる、もしくは計
時、計算機能をも含むICチツプで前述した方法
により、回路基板１１上に加熱圧着されている。
１３は液晶表示体１０と回路基板１１とをやはり
加熱圧着する加熱融着性を有する導体配線部であ
る。 FIG. 3 shows an actual application example of the present invention, in which the above circuit board is applied to a liquid crystal display. 10 is a liquid crystal display, 11 is a circuit board based on the present invention, 12
is an IC chip that drives the liquid crystal display 10 or has time measurement and calculation functions, and is heat-pressed onto the circuit board 11 by the method described above.
Reference numeral 13 denotes a conductive wiring portion having heat-fusion bonding properties for bonding the liquid crystal display 10 and the circuit board 11 together under heat and pressure.
本具体例の場合、液晶表示体はガラス基板から
なり、電極は酸化錫、酸化インジウム等からなり
直接ハンダ付けができない。又導電ゴム等で、プ
リント配線基板と電気接続する方法もあるが、こ
の場合、押圧部品が必要となると共に、実装体積
も増えてしまう。本発明によれば、回路基板が前
述した様にヒートシール型の回路基板である為直
接、液晶表示体に回路基板を加熱圧着により電気
接続ができる。 In the case of this specific example, the liquid crystal display body is made of a glass substrate, and the electrodes are made of tin oxide, indium oxide, etc., and cannot be directly soldered. There is also a method of electrically connecting to the printed wiring board using conductive rubber or the like, but in this case, pressing parts are required and the mounting volume increases. According to the present invention, since the circuit board is a heat seal type circuit board as described above, it is possible to electrically connect the circuit board directly to the liquid crystal display by heat-pressing bonding.
かかる本発明のICチツプ付き回路基板によれ
ば、ICチツプは電極パツド部に基板との接合用
のためのバンプを形成する等の特別な方法を行な
わなくてもICチツプと基板との電気的接合が行
なえる。この際ICチツプの電極パツドと基板の
導電配線部とが導電接着層を介した接着によつて
行なわれるが、ICチツプと基板とは、ICチツプ
の電極パツドで囲まれた部分と基板との間に設け
られた絶縁体の熱融着層によつても機械的な接合
が行なわれるため、ICチツプと基板との電気的
接合が導電接着層を介して行なわれるにもかかわ
らずその電気的接合の信頼性を大変高めることが
できる。さらに、このようなICチツプ付きの回
路基板を用いるとICチツプを直接ハンダ付けに
よつて液晶パネル上にフエースダウンボンデイン
グする必要がなく、ICチツプを搭載した回路基
板を導電配線部を介して液晶パネルに熱融着させ
ればよく、ハンダ付けに比べて非常に低温でIC
チツプを搭載した液晶表示装置を構成でき、液晶
パネルの配向を劣化させ、液晶パネルの表示品質
や、寿命に悪影響を与えることがない。また、液
晶パネルの電極が透明性にすぐれ表示用に適して
いるが、ハンダ付けができず、電極パツド上のハ
ンダバンプによるフエースダウンボンデイング
が、一般的に不可能なものであつても、本発明の
ように構成したICチツプ付き回路基板を使用す
ることにより、ICチツプを液晶パネルと一体化
し、電気的接続の非常に高い液晶表示装置を簡単
に構成することができる。 According to the circuit board with an IC chip of the present invention, the IC chip can be electrically connected to the board without any special method such as forming bumps for bonding with the board on the electrode pad portion. Can be joined. At this time, the electrode pads of the IC chip and the conductive wiring portion of the substrate are bonded together via a conductive adhesive layer, but the IC chip and the substrate are Mechanical bonding is also achieved by the heat-sealing layer of insulator provided between the IC chips and the substrate, so even though the electrical bonding between the IC chip and the substrate is done through the conductive adhesive layer, the electrical The reliability of bonding can be greatly improved. Furthermore, by using such a circuit board with an IC chip, there is no need to bond the IC chip face-down onto the liquid crystal panel by direct soldering. All you have to do is heat-fuse the IC to the panel, and the IC can be soldered at a much lower temperature than soldering.
It is possible to configure a liquid crystal display device equipped with a chip, and the alignment of the liquid crystal panel will not be deteriorated and the display quality and life of the liquid crystal panel will not be adversely affected. Further, even if the electrodes of a liquid crystal panel have excellent transparency and are suitable for display purposes, but cannot be soldered and face-down bonding using solder bumps on the electrode pads is generally impossible, the present invention By using a circuit board with an IC chip configured as described above, the IC chip can be integrated with a liquid crystal panel, and a liquid crystal display device with extremely high electrical connectivity can be easily constructed.
第１図は、本発明のICチツプ付き回路基板の
断面図で、１は回路基板、２，３は加熱融着性を
有する導体配線部、４，５，６はやはり加熱融着
性を有する絶縁接着層である。第２図は、本発明
に基づくICチツプ付き回路基板の実施例で、７
はICチツプ、８はICチツプのパツド部である。
第３図は、本発明のICチツプ付き回路基板の液
晶表示装置への応用例で、１０は液晶表示体、１
２はICチツプである。
FIG. 1 is a cross-sectional view of a circuit board with an IC chip of the present invention, in which 1 is a circuit board, 2 and 3 are conductor wiring parts that have heat-fusibility, and 4, 5, and 6 also have heat-fusibility. It is an insulating adhesive layer. Figure 2 shows an embodiment of a circuit board with an IC chip based on the present invention.
8 is the IC chip, and 8 is the pad part of the IC chip.
FIG. 3 shows an example of application of the circuit board with an IC chip of the present invention to a liquid crystal display device, in which 10 is a liquid crystal display body, 1
2 is an IC chip.
Claims (1)
た液晶パネルを表示駆動するICチツプが搭載さ
れ、前記液晶パネルと一体化される回路基板にお
いて、 前記回路基板上には導電性粒子と熱融着樹脂と
からなり前記液晶パネルと熱融着接合される導電
配線部が形成され、 電極パツド面を前記回路基板に対向配置した前
記ICチツプの前記電極パツドに対応した前記導
電配線部上には前記導電性粒子と熱融着樹脂とか
らなる導電接着層が積層形成され、 前記導電接着層の熱融着により前記電極パツド
が前記導電配線部に接合されると共に、 前記導電接着層に囲まれた前記回路基板面上に
は絶縁体の熱融着層が印刷形成され、該熱融着層
により前記ICチツプの前記電極パツドに囲まれ
た部分と前記回路基板とが熱融着接合されること
を特徴とするICチツプ付き回路基板。[Scope of Claims] 1. A circuit board on which an IC chip for displaying a liquid crystal panel whose electrodes are formed of tin oxide or indium oxide is mounted and is integrated with the liquid crystal panel, wherein a conductive layer is provided on the circuit board. A conductive wiring portion is formed of particles and a heat-sealing resin and is heat-sealed and bonded to the liquid crystal panel, and the conductive wiring corresponds to the electrode pad of the IC chip with the electrode pad surface facing the circuit board. A conductive adhesive layer made of the conductive particles and a heat-sealing resin is laminated on the part, and the electrode pad is joined to the conductive wiring part by heat-sealing the conductive adhesive layer, and the conductive adhesive layer is bonded to the conductive wiring part. A heat-sealing layer of an insulator is printed on the surface of the circuit board surrounded by the layers, and the heat-sealing layer heat-fuses the portion of the IC chip surrounded by the electrode pads and the circuit board. A circuit board with an IC chip that is bonded together.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13046479A JPS5654091A (en) | 1979-10-09 | 1979-10-09 | Electric circuit unit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13046479A JPS5654091A (en) | 1979-10-09 | 1979-10-09 | Electric circuit unit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5654091A JPS5654091A (en) | 1981-05-13 |
| JPS6245999B2 true JPS6245999B2 (en) | 1987-09-30 |
Family
ID=15034856
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13046479A Granted JPS5654091A (en) | 1979-10-09 | 1979-10-09 | Electric circuit unit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5654091A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60133789A (en) * | 1983-12-21 | 1985-07-16 | 株式会社精工舎 | Circuit board and method of producing same |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5725248Y2 (en) * | 1977-01-18 | 1982-06-01 |
-
1979
- 1979-10-09 JP JP13046479A patent/JPS5654091A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5654091A (en) | 1981-05-13 |
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