JPS6245213A - Synchronization system for asynchronizing signal - Google Patents

Abstract

PURPOSE:To obtain a stable synchronizing signal with a simple circuit by providing a means selecting a clock to an FF circuit to which an asychronizing signal is applied in a cynchronizing system using 2-stages of the FF circuits. CONSTITUTION:A multiplex circuit 3 operated as a selection circuit is added to a clock terminal of the FF circuit 1. The multiplex circuit 3 is operated by depressing, e.g., a switch 3-1 by the operator while a double CLK controls the Ff circuit 1. If the FF circuit 1 has a large instable operation region and an undesired output is caused at a synchronizing signal D3 as an output of the FF circuit 2, the multiplex circuit 3 is changed over by the switch 3-1 to operate it by a CLK. Since the next clock is given to the instable operating region in this way, no undesired signal appears at the synchronizing signal D3. Thus, a stable synchronizing signal is obtained by a simple circuit.

Description

[Detailed Description of the Invention] [Summary] This is an asynchronous signal synchronization method in which the asynchronous signal is received by a first flip-flop circuit, and the output of the first flip-flop circuit is converted into a synchronous signal by a second flip-flop circuit. In this case, a circuit is provided to select the clock of the first flip-flop circuit, and a stable lock signal is output to iJ.
7.

[Industrial application field]

The present invention relates to an asynchronous signal synchronization method for synchronizing asynchronous signals.

2. Description of the Related Art A method for extracting a peering signal from an asynchronous signal is widely used in fields such as information processing and communications. As one of them, 2
Some use stage flip-flop circuits. on the other hand,
In order to increase the processing speed of the device, there is a need for a synchronization method for asynchronous signals that can easily obtain a normal synchronization signal.

[Conventional technology]

Conventionally, a synchronization method using two-stage flip-flop circuits has been implemented in the circuits shown in FIGS. 2 and 3. That is, the asynchronous signal D1 is input to the flip-flop circuit 1, and the output D2 of the flip-flop circuit I is input to the second flip-flop circuit 2. The synchronization required by the output D3 of the second flip-flop circuit 2 is the i-th D3.

The difference between FIG. 2 and FIG. 3 is the clock signal that controls the first free-flow/two-block circuit 1. FIG. 2 shows the clock C that controls the second flip-flop circuit PΣ;
The first flip flow knob circuit 1 is controlled at L I<;
J+), FIG. 3 is controlled by twice the clock 2CLK.

In the case of the clock CLK shown in FIG. 2, it operates with the 1" whip shown in FIG.
In the case of LK, it operates at time chart 1 shown in Fig. 5).

That is, when the fall of the clock CLK (2CLK) and the rise of the asynchronous signal Di match, the output signal D2 of the flip-flop circuit 1 becomes unstable for a while as shown in part A shown in the figure. When the unstable state becomes stable and the logic becomes ``1'' or ``O'', the flip-flop circuit 2 can obtain the synchronizing signal D3 in 2 cycles (1 and 5 cycles)6. If the clock is increased or there are variations in the circuit elements used when the synchronization signal D3 is in the opposite direction, as shown in FIG. 6, an unstable state occurs when the synchronization signal D3 is 1.5 cycles. If,
If this 1.5 cycle signal is used in other parts of the device, a problem will occur, so the processing speed must be slowed down.

[Problem that the invention seeks to solve]

In the conventional system, in order to improve the processing speed, the clock is made faster, and due to the influence of the circuit elements, it is sometimes impossible to obtain the initially intended synchronization signal.

The present invention was created in view of these points, and an object of the present invention is to provide a synchronization method for asynchronous signals that can obtain stable synchronization signals with a simple configuration.

(Means for solving the problem) A first flip-flop circuit is provided with a selection circuit for selecting a clock.

[Effect]

The selection circuit selects the second 797171371 circuit input and double clock, and operates the first Frisobuf knob circuit with the selected clock. In the present invention, when increasing the clock speed, the synchronization signal g can be controlled simply by selecting double click using the selection circuit.

〔Example〕

FIG. 1 is a schematic diagram of an embodiment of the present invention, in which a multi-nox circuit 3 operating as a selection circuit is attached to the clock terminal of a flip-flop circuit 1.

Multiplex episode! ? The input of 83 is the same clock CLK as the clock CLK of the second flip-flop circuit 2 and CL which is twice the clock CLK. The operation of the multiplex circuit 3 is such that the operator presses the switch 3-1, for example, so that the double CLK controls the first free-seven block circuit 1.

Therefore, when operating at <2C1, as shown in Figure 6,
When the flip-flop circuit 1 has a large unstable operation region and an undesired output is generated at D3 as the output of the flip-flop circuit 2, the multiplex circuit 3 is switched to switch 3.
Switch with -1 and operate with CLK. If this is done, the operation will be substantially similar to that shown in FIG. 5, and since the next clock will not enter the unstable operation region, 2, an undesired signal will not appear on D3. Moreover, the processing speed can be changed only with one switch.

〔Effect of the invention〕

As described above, according to the present invention, the processing speed is changed based on stability with an extremely simple configuration, and is extremely effective in changing the I-cock.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2 is a block diagram of a conventional ICL, Fig. 3 is a block diagram of a conventional ICL clock, and Fig. 4 is a time error diagram of a conventional ICLK.・Yards. Figure 5 shows the time chart 1 at 2 CLK, and Figure 6 shows the time chart when the black and 7 are made faster. In the figure, 1 and 2 are flip-flop circuits of the present invention. 7CLK call 0.77 Figure 3 Figure 7 CLKG hands 7 Buddhas ``w) 4 Figure 2CL, Nigin et al. 7 to LL< to 8 to 714-r-f-Figure 6

Claims (1)

[Claims] A first flip-flop circuit (1
) and a second flip-flop circuit (1) that receives the output of the first flip-flop circuit (1) and creates a synchronization signal.
2), and the first flip-flop circuit (1
) includes a selection circuit (3) for selecting a clock, and selects the clock of the second flip-flop circuit (2) and a clock twice as high as the clock of the first flip-flop circuit (1). A synchronization method for asynchronous signals.