JPS6240840A - Transmitting/receiving circuit for data terminal equipment - Google Patents

Transmitting/receiving circuit for data terminal equipment

Info

Publication number
JPS6240840A
JPS6240840A JP60180575A JP18057585A JPS6240840A JP S6240840 A JPS6240840 A JP S6240840A JP 60180575 A JP60180575 A JP 60180575A JP 18057585 A JP18057585 A JP 18057585A JP S6240840 A JPS6240840 A JP S6240840A
Authority
JP
Japan
Prior art keywords
serial data
transmitting
transmitting serial
byte
bit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60180575A
Other languages
Japanese (ja)
Inventor
Nobuyuki Sato
Takashi Koitabashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP60180575A priority Critical patent/JPS6240840A/en
Publication of JPS6240840A publication Critical patent/JPS6240840A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To obtain a transmitting serial data being in a state that it is brought to a character alignment while matching the byte and bit of a receiving serial data by adding a means having a character alignment function.
CONSTITUTION: When a send gate open signal is in an on-state, if a transmitting serial data is inputted to an STP 15, the STP 15 sends a stop pulse to a counter 17. The transmitting serial data inputted to a shift register 16 is shifted and sent to a data selector 18. In this case, a selector data corresponding to the shifted input transmitting serial data synchronized with a receiving serial data as to its bit and byte is selected. In this way, the transmitting serial data brought to a character alignment while matching the bit and byte can be outputted from the selector 18.
COPYRIGHT: (C)1987,JPO&Japio
JP60180575A 1985-08-19 1985-08-19 Transmitting/receiving circuit for data terminal equipment Pending JPS6240840A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60180575A JPS6240840A (en) 1985-08-19 1985-08-19 Transmitting/receiving circuit for data terminal equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60180575A JPS6240840A (en) 1985-08-19 1985-08-19 Transmitting/receiving circuit for data terminal equipment

Publications (1)

Publication Number Publication Date
JPS6240840A true JPS6240840A (en) 1987-02-21

Family

ID=16085672

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60180575A Pending JPS6240840A (en) 1985-08-19 1985-08-19 Transmitting/receiving circuit for data terminal equipment

Country Status (1)

Country Link
JP (1) JPS6240840A (en)

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