JPS6238354Y2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to an electric field strength detection circuit, in which a signal passed through a predetermined intermediate frequency circuit, either a wideband intermediate frequency circuit or a narrowband intermediate frequency circuit, is used in an FM stereo radio receiver, etc. To provide an electric field strength detection circuit capable of accurately detecting electric field strength without causing a detection error due to a difference in gain characteristics between the two intermediate frequency circuits by detecting the level of the intermediate frequency circuit and detecting the electric field strength. The purpose is to

Conventional FM stereo radio receivers with an intermediate frequency band switching function share a wideband intermediate frequency circuit and a narrowband intermediate frequency circuit in order to limit the frequency band of the sideband of the intermediate frequency depending on the reception situation. , the user selects either one using a manual key depending on the reception situation at the reception point. For example, if there are many FM reception frequencies and interference from adjacent signals is large, narrowband intermediate frequency circuits are selected and used;
When the FM reception frequency is small, a wideband intermediate frequency circuit with excellent audio characteristics such as distortion and separation is selected and used.

In such a circuit configuration, when detecting the electric field strength by detecting the level of the intermediate frequency (for example, 10.7MHz), the wideband intermediate frequency circuit and the narrowband intermediate frequency circuit have different gain characteristics. There is a disadvantage in that a difference occurs in level between the intermediate frequency that has passed through the narrowband intermediate frequency circuit and the intermediate frequency that has passed through the narrowband intermediate frequency circuit, and this level difference results in an error during detection. In order to eliminate this drawback, there have been cases in the past in which a new intermediate frequency band filter exclusively for electric field strength detection was provided, but this had the drawbacks of increasing costs and complicating the circuit.

The present invention aims to eliminate the above-mentioned drawbacks, and one embodiment thereof will be described with reference to the drawings.

The FM signal that enters terminal 1 is sent to mixing circuit 2.
The frequency is converted to an intermediate frequency of 10.7MHz, and this intermediate frequency signal is sent to a gate circuit 15 or 16, which will be described later.
and is supplied to either the narrowband intermediate frequency circuit 3 or the wideband intermediate frequency circuit 4. The intermediate frequency signal whose sideband frequency band is limited by the narrowband intermediate frequency circuit 3 or the wideband intermediate frequency circuit 4 is transmitted to the first stage intermediate frequency amplification circuit 5, the second stage intermediate frequency amplification circuit 6, and the third stage intermediate frequency amplification circuit 6. The signal passes through the intermediate frequency amplification circuit 7, is amplified at each stage, and is supplied to the detection circuit 8. The detection circuit 8 performs FM detection on the amplified intermediate frequency signal and outputs it from a terminal 9 as a stereo composite signal.

On the other hand, the output of each intermediate frequency amplification circuit 5, 6, 7 is supplied to a level detector 10.
0 converts the level of the input intermediate frequency signal of 10.7 MHz to the DC voltage level and supplies it to the A/D converter 11. The A/D converter 11 reads the DC voltage level from the level detector 10, converts it into a digital value, and supplies it to a digital tuning system controller 12 (hereinafter referred to as a DTS controller).

The DTS controller 12 is an A/D converter 11
The digital value is read and digitally displayed as the electric field strength of the intermediate frequency signal. Or each
The electric field strength at the intermediate frequency of the FM frequency is stored for each FM frequency channel.

Next, the opening and closing of the gate circuits 15 and 16 described above will be explained. Methods for instructing switching between opening and closing of the gate circuits 15 and 16 include (1) manual switching instruction, (2) forced switching instruction when the DTS controller 12 requests electric field strength detection data, and (3)
When the preset station in the DTS controller 12 is designated as wideband or narrowband, there are three switching instructions depending on the designation.

First, a case where a switching instruction is given by manual operation will be explained. Output terminal a of DTS controller 12
A high level is output from the output terminal b, a low level is output from the output terminal c, and a low level is output from the output terminal c. The switch 18 is a switch that, when the operator presses the switch 18, always switches the terminals e→d→e. As long as the operator does not press the switch, it is always switched to the terminal e side, so the +5V voltage coming into terminal 17 is
It is supplied to the R terminal of the SR flip-flop 19. When the operator presses the switch, this +
A voltage of 5V is supplied to the S terminal of the SR flip-flop 19 as a trigger signal. When a trigger signal is supplied to the S terminal of the SR flip-flop 19,
The output state of the Q terminal changes, for example, outputs a high level signal and supplies it to the flip-flop 20. When a high level signal is supplied to the CK terminal of the flip-flop 20, the state of the Q terminal is inverted and, for example, if the previous state was high level, it is outputted to a low level and is supplied to the NAND circuit 13. here,
The S terminal of the flip-flop 20 is supplied with a low-level signal from the output terminal b of the DTS controller 12, and the R terminal is supplied with a low-level signal from the output terminal c, and the output of the flip-flop 20 is supplied to the D input terminal. It is connected to the.

The NAND circuit 13 is connected to the Q of the flip-flop 20.
When the terminal is at a low level, it receives a low level signal from the flip-flop 20 and outputs a high level signal, and the gate circuit 16 is opened by this high level signal. At the same time, the high level signal from the NAND circuit 13 is inverted to low level by the inverting circuit 14, and the gate circuit 15 is closed by this low level signal. In this way, the intermediate frequency signal from the mixing circuit 2 is supplied to the broadband intermediate frequency circuit 4 via the gate circuit 16. When the operator switches the switch 18 again, a low level signal is supplied to the gate circuit 16, which closes this circuit, and a high level signal is supplied to the gate circuit 15, which opens and outputs the intermediate frequency signal. is supplied to the narrow band intermediate frequency circuit 3 via the gate circuit 15. In this way, each time the switch 18 is pressed, the gate circuit 15 or the gate circuit 16 can be alternately opened and closed.

Next, when the DTS controller 12 requests electric field strength detection data, the gate circuits 15 and 16
The forced switching instruction will be explained below. this is,
As described above, in order to display the level of the electric field strength detected by the level detector 10, the DTS controller 12 unilaterally selects either the wideband intermediate frequency circuit 4 or the narrowband intermediate frequency circuit 3. , which displays the level of the signal that has passed through the selected circuit. In this embodiment, for example, the wideband intermediate frequency circuit 4 is unilaterally selected.
First, the DTS controller 12 turns on muting (not shown) and then supplies a low level signal to the NAND circuit 13 from the output terminal a.
The NAND circuit 13 outputs a high level regardless of the level of the Q output from the flip-flop 20, and this high level signal causes the gate circuit 1 to
6 will be held. On the other hand, the high level signal is also supplied to the inverter 14, inverted, and supplied as a low level signal to the gate circuit 15, so that the gate circuit 15 is closed. In this way, the intermediate frequency signal from the mixing circuit 2 passes through the wideband intermediate frequency circuit 4, the intermediate frequency amplifiers 5, 6, 7, and the level detector 10, and the DC level corresponding to the electric field strength is detected by the A/D converter. 11 , it is converted into a digital value and supplied to the DTS controller 12 . DTS
After displaying the field strength based on this data, the controller 12 outputs a high level from the output terminal a, returns to the intermediate frequency band before the field strength detection, and turns off muting. In this way, when detecting the electric field strength, the intermediate frequency signal from only the wideband intermediate frequency circuit 4 is obtained, and the electric field strength is detected. Since there is no doubt whether to detect the electric field strength of the intermediate frequency of the two, and therefore no error occurs due to the gain characteristics of the two, the electric field strength can always be detected and displayed accurately.

Furthermore, when the station preset in the DTS controller 12 is designated as wideband or narrowband, instructions for switching the gate circuits 15 and 16 to open or close based on the designation will be explained. First, it is assumed that the preset station is designated as a narrow intermediate frequency band. When the DTS controller 12 receives an instruction and calls this preset station, the DTS controller 12 outputs a high level signal from the output terminal b. Therefore, since a high level signal is supplied to the S terminal of the flip-flop 20, the flip-flop 20 supplies a high level signal to the NAND circuit 13 from the Q terminal. Further, since the input signal from the output terminal a of the DTS controller 12 to the NAND circuit 13 is at a high level, the NAND circuit 13 supplies a low level signal to the gate circuit 16, and the gate circuit 16 is closed. At the same time, the low level signal of the NAND circuit 13 is also supplied to the inverter 14, inverted, and supplied as a high level signal to the gate circuit 15.
5 will be opened. In this way, the intermediate frequency signal is supplied to the narrowband intermediate frequency circuit 3 via the gate circuit 15.

Next, assume that the preset station is designated to a wide intermediate frequency band. When the DTS controller 12 receives an instruction and calls this preset station, the DTS controller 12 outputs the output terminal c.
Outputs a higher level signal. Therefore, since a high level signal is supplied to the R terminal of the flip-flop 20, the flip-flop 20 supplies a low level signal to the NAND circuit 13 from its Q terminal. Further, since the input signal from the output terminal a of the DTS controller 12 to the NAND circuit 13 is at a high level as described above, the NAND circuit 13 supplies a high level signal to the gate circuit 16, and the gate circuit 16 is opened. . Also, at the same time, the NAND circuit 13
The high-level signal is also supplied to the inverter 14, inverted, and sent to the gate circuit 1 as a low-level signal.
5 and the gate circuit 15 is closed. In this way, the intermediate frequency signal is supplied to the broadband intermediate frequency circuit 4 via the gate circuit 16.

In this embodiment, the intermediate frequency signal is forcibly supplied to the wideband intermediate frequency circuit 4 when detecting the electric field strength, but it may be supplied to the narrowband intermediate frequency circuit 3.

As mentioned above, the electric field strength detection circuit according to the present invention is
a circuit that detects the electric field strength by detecting the level of the signal that has passed through the wideband intermediate frequency circuit or the narrowband intermediate frequency circuit; Since the configuration includes a circuit that controls the switching circuit so as to supply a frequency signal, when detecting the electric field strength, the level of the signal that has passed only through either the wideband intermediate frequency circuit or the narrowband intermediate frequency circuit is detected. Since the electric field strength can be detected using the above-described method, there is no error in detecting the electric field strength due to the difference in the gain characteristics of the two intermediate frequency band circuits, and therefore the electric field strength can be detected with high accuracy. .

[Brief explanation of the drawing]

The figure is a circuit system diagram showing one embodiment of the electric field strength detection circuit of the present invention. 2... Mixing circuit, 3... Narrowband intermediate frequency circuit, 4... Wideband intermediate frequency circuit, 8... Detection circuit, 10... Level detector, 11... A/D converter, 12... Digital tube ning system controller (DTS controller), 15, 16...
Gate circuit, 19, 20... flip-flop.

Claims (1)

[Scope of utility model registration request] A radio receiver comprising a wideband intermediate frequency circuit and a narrowband intermediate frequency circuit, and a switching circuit that selectively supplies an intermediate frequency signal to either one of the two intermediate frequency circuits. a circuit that detects the electric field strength by detecting the level of the signal that has passed through the band intermediate frequency circuit;
An electric field strength detection circuit comprising: a circuit for controlling the switching circuit so as to supply the intermediate frequency signal to a predetermined one of the two intermediate frequency circuits during electric field strength detection.