JPS6237930A - Electron beam exposing method - Google Patents

Electron beam exposing method

Info

Publication number
JPS6237930A
JPS6237930A JP17796385A JP17796385A JPS6237930A JP S6237930 A JPS6237930 A JP S6237930A JP 17796385 A JP17796385 A JP 17796385A JP 17796385 A JP17796385 A JP 17796385A JP S6237930 A JPS6237930 A JP S6237930A
Authority
JP
Japan
Prior art keywords
resist film
electron beam
pattern
resist
electron
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17796385A
Other languages
Japanese (ja)
Inventor
Yasuhiro Takasu
高須 保弘
Yoshihiro Todokoro
義博 戸所
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP17796385A priority Critical patent/JPS6237930A/en
Publication of JPS6237930A publication Critical patent/JPS6237930A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To form a fine pattern with high dimensional accuracy, by forming a resist pattern whose cross-sectional form is nearly vertical, by a method wherein the distribution of the electron absorption energy in a resist film is made uniform by the effect of a dual exposure applying both a high acceleration voltage and a low acceleration voltage. CONSTITUTION:After a resist film 6 sensitive to electron beams is coated on a semiconductor substrate 3, a predefined pattern is drawn on a resist film 6 by electron beams with acceleration voltage to penetrate the resist film 6. Then, the pattern is drawn on the resist film 6 by the electron beams 8 with acceleration voltage insufficient to penetrate the resist film 6. Thus the distribution of electron absorption energy in the resist film 6 is made uinform. Thereby, resist pattern 9 whose cross-sectional form is nearly vertical is formed, and a fine pattern with high dimensional accuracy is obtained.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は二重露光により寸法精度のよい微細なレジスト
パターンを形成する電子ビーム露光方法に関するもので
ある。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an electron beam exposure method for forming fine resist patterns with good dimensional accuracy by double exposure.

従来の技術 近年、半導体基板内に作り込まれる半導体素子の微細化
、高集積化を図るにあたり、微細パター2ベージ ンを形成するのに適している電子ビーム露光方法が用い
られている。
2. Description of the Related Art In recent years, in an effort to miniaturize and increase the integration of semiconductor elements built into semiconductor substrates, an electron beam exposure method suitable for forming a fine pattern 2 basis has been used.

この電子ビーム露光方法は、半導体基板上に電子に反応
するレジスト膜(感電子線レジスト膜)を塗布した後、
コンピュータで電子ビームの走査を制御することにより
レジスト膜上に所定のパターンを描画し、この後、現像
処理を施こして所定のレジストパターンを半導体基板上
に形成する方法である。第2図はこの方法で露光したレ
ジスト膜中の等エネルギー線による電子吸収エネルギー
量の分布曲線であり、レジスト膜1に入射された電子ビ
ーム2がレジスト膜1中を通過し、シリコン基板3表面
に達した電子はシリコン基板3により散乱されるため、
レジスト膜内部の電子吸収エネルギー量は、シリコン基
板3表面に近づくにつれて大きくなり、しかも、電子吸
収エネルギー量の分布曲線は、シリコン基板3表面に沿
って水平方向に広がった傾向を示す。
In this electron beam exposure method, after applying a resist film that reacts to electrons (electron beam sensitive resist film) on a semiconductor substrate,
This is a method in which a predetermined pattern is drawn on a resist film by controlling the scanning of an electron beam using a computer, and then a development process is performed to form a predetermined resist pattern on a semiconductor substrate. FIG. 2 is a distribution curve of the amount of electron absorption energy due to isoenergetic lines in the resist film exposed by this method. The electron beam 2 incident on the resist film 1 passes through the resist film 1, and the Since the electrons that have reached are scattered by the silicon substrate 3,
The amount of electron absorption energy inside the resist film increases as it approaches the surface of the silicon substrate 3, and the distribution curve of the amount of electron absorption energy shows a tendency to spread horizontally along the surface of the silicon substrate 3.

発明が解決しようとする問題点 このような傾向の下で露光がなされたレジスト3へ−7 膜を現像した後のレジストパターンの断面図を第3図に
示す。第3図aはシリコン基板3上にポジレジスト4を
塗布した場合であり、電子ビーム2が照射された領域の
レジスト膜が除去され、しかも、レジスト膜のシリコン
基板側が多く除かれたアンダーカット形状となる。第3
図すはシリコン基板1の上にネガレジスト6を塗布した
場合であり、電子ビーム2が照射された領域のレジスト
が残り、しかも、断面が台形の形状となる。いずれの場
合においても寸法精度が低いパターン形状となる不都合
が生じる。
Problems to be Solved by the Invention FIG. 3 shows a cross-sectional view of the resist pattern after developing the resist 3-7 film exposed under such a tendency. FIG. 3a shows a case where a positive resist 4 is applied on a silicon substrate 3, and the resist film in the area irradiated with the electron beam 2 is removed, and moreover, it has an undercut shape in which much of the silicon substrate side of the resist film is removed. becomes. Third
The figure shows a case where a negative resist 6 is applied on a silicon substrate 1, and the resist remains in the area irradiated with the electron beam 2, and has a trapezoidal cross section. In either case, the problem arises that the pattern shape has low dimensional accuracy.

問題点を解決するだめの手段 本発明の電子ビーム露光方法は、レジスト膜内部の電子
吸収エネルギー分布を均一にして、側面が基板に対して
ほぼ垂直な形状となるレジストパターンを形成すること
を目的とするものであって、牛導体基板上に感電子線レ
ジスト膜を塗布した後、前記感電子線レジスト膜を貫通
する加速電圧の電子線を用いて、所定パターンを前記感
電子レジスト膜上に描画する第1の露光と、前記感電子
線レジスト膜を貫通することのない加速電圧の電子線を
用いて、前記パターンを前記感電子線レジスト膜上に描
画する第2の露光を備えるものである。
Means to Solve the Problems The electron beam exposure method of the present invention aims to make the electron absorption energy distribution within the resist film uniform, and to form a resist pattern whose side surfaces are approximately perpendicular to the substrate. After applying an electron beam sensitive resist film on a conductor substrate, a predetermined pattern is formed on the electron beam sensitive resist film using an electron beam at an accelerating voltage that penetrates the electron beam sensitive resist film. The method comprises a first exposure for drawing, and a second exposure for drawing the pattern on the electron beam-sensitive resist film using an electron beam at an accelerating voltage that does not penetrate the electron-beam-sensitive resist film. be.

作用 この電子ビーム露光方法では、レジスト膜を貫通する加
速電圧の電子線で露光した後、レジスト膜表面で電子吸
収エネルギーが大きく、レジスト膜を貫通することのな
い加速電圧の電子線で重畳して露光するため、レジスト
膜内の電子吸収エネルギーの分布を均一にすることがで
きる。
Function: In this electron beam exposure method, after exposing the resist film with an electron beam at an accelerating voltage that penetrates the resist film, the electron beam is superimposed with an accelerating voltage that does not penetrate the resist film because the electron absorption energy is large on the resist film surface. Since the resist film is exposed to light, the distribution of electron absorption energy within the resist film can be made uniform.

実施例 本発明の電子ビーム露光方法の実施例を第1図の工程流
れ図を参照して説明する。
Embodiment An embodiment of the electron beam exposure method of the present invention will be described with reference to the process flowchart of FIG.

まず、シリコン基板3上に東洋ソーダ(株)から商品名
CMS−Exとして市販されている電子ビーム用ネガレ
ジスト(クロロメチル化ポリスチレン樹脂)(以下0M
Sレジストと記す)6を0.6μmの厚さに塗布し、1
30℃の温度で30分間のプリベークを行う(第1図Δ
) つぎに、このレジスト膜厚を貫通する加速電圧5x、−
/゛ が20KVの電子ビーム7の走査をコンピュータで制御
しながら0MSレジスト膜6の上に6μO/cAの露光
量で所定パターン全描画する(第1図b)。
First, a negative resist for electron beam (chloromethylated polystyrene resin) (hereinafter referred to as 0M polystyrene resin) commercially available from Toyo Soda Co., Ltd. under the trade name
S resist) 6 was applied to a thickness of 0.6 μm, and 1
Pre-bake for 30 minutes at a temperature of 30°C (Fig. 1 Δ
) Next, the acceleration voltage 5x, - which penetrates this resist film thickness is
A predetermined pattern is entirely drawn on the OMS resist film 6 at an exposure dose of 6 μO/cA while controlling the scanning of the electron beam 7 with a voltage of 20 KV by a computer (FIG. 1b).

つづいて、加速電圧が6KYの電子ビーム8の走査をコ
ンピュータで制御しながら0MSレジスト膜6上に2μ
Q/cAの露光量で同一パターンを描画する(第1図C
)。
Next, while controlling the scanning of the electron beam 8 with an acceleration voltage of 6KY by a computer, a 2μ
Draw the same pattern with an exposure amount of Q/cA (Fig. 1C
).

ここで加速電圧が5KVにおける0MSレジスト膜中の
電子ビームの入射方向の電子吸収エネルギー分布を下表
に示す。
Here, the electron absorption energy distribution in the incident direction of the electron beam in the OMS resist film at an accelerating voltage of 5 KV is shown in the table below.

(以下余白) 6   、 加速電圧が5KVでは、0.6μmの深さまで′電子が
侵入するものの、レジスト膜表面から深くなるに従って
減少していき、0.6μmより深くなると侵入する電子
は存在しなくなる。したがってレジスト膜厚を0.6μ
mf:越える厚さに選定しておくと、シリコン基板3か
ら反則された電子が散乱されることはない。捷だ、表面
で電子吸収エネルギーが大きいため表面近傍で表面散乱
により電子吸収エネルギー分布は水平方向に広がる。し
たがって、加速電圧が20KVの電子吸収エネルギー分
布に、加速電圧が5KVの電子吸収エネルギー分布を重
畳することにより、レジスト膜表面よりシリコン基板ま
でほぼ均一な電子吸収エネルギー分布を得ることができ
る。
(Left below) 6. When the accelerating voltage is 5 KV, electrons penetrate to a depth of 0.6 μm, but the number decreases as the depth increases from the resist film surface, and when the depth becomes deeper than 0.6 μm, there are no penetrating electrons. . Therefore, the resist film thickness should be set to 0.6μ.
If a thickness exceeding mf is selected, electrons rejected from the silicon substrate 3 will not be scattered. Because the electron absorption energy is large at the surface, the electron absorption energy distribution spreads horizontally due to surface scattering near the surface. Therefore, by superimposing the electron absorption energy distribution with an accelerating voltage of 5 KV on the electron absorption energy distribution with an accelerating voltage of 20 KV, it is possible to obtain a substantially uniform electron absorption energy distribution from the resist film surface to the silicon substrate.

このように均一な電子吸収エネルギー分布をもったcM
sレジスト膜6を酢酸イソアミルとエチルセルソルブニ
が1:3の割合の現像液を用いて1分間現像し、イソプ
ロピルアルコールで1分間リンスすることにより、電子
ビームを照射した領域に断面形状がほぼ垂直なレジスト
パターン9を得ることができる(第1図d)。
In this way, cM with a uniform electron absorption energy distribution
s The resist film 6 is developed for 1 minute using a developer containing isoamyl acetate and ethyl cellulone in a ratio of 1:3, and rinsed for 1 minute with isopropyl alcohol, so that the cross-sectional shape is approximately the same in the area irradiated with the electron beam. A vertical resist pattern 9 can be obtained (FIG. 1d).

なお、実施例では電子の加速電圧が20蒔と5肝の例を
掲げたがこの値は、レジストの種類や膜厚等により変化
するのであって、レジスト膜を貫通する加速電圧とレジ
スト膜を貫通することのない加速電圧であればよい。
In addition, in the example, an example is given in which the electron acceleration voltage is 20 Ω and 5 Ω, but this value varies depending on the type of resist, film thickness, etc., and the acceleration voltage that penetrates the resist film and the resist film Any accelerating voltage that does not penetrate can be used.

発明の効果 本発明の電子ビーム露光方法によれば、レジスト膜を貫
通する高加速電圧とレジスト膜を貫通することのない低
加速電圧による二重露光により、レジスト膜内部の電子
吸収エネルギー分布を均一にして、断面形状がほぼ垂直
々レジストパターンを形成し、寸法精度の高い微細パタ
ーンを形成することができる。
Effects of the Invention According to the electron beam exposure method of the present invention, double exposure using a high accelerating voltage that penetrates the resist film and a low accelerating voltage that does not penetrate the resist film makes the electron absorption energy distribution inside the resist film uniform. In this way, a resist pattern with a substantially vertical cross-sectional shape can be formed, and a fine pattern with high dimensional accuracy can be formed.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の電子ビーム露光方法における法による
レジストパターンの断面図である。 3・・・・・・シリコン基板、6・・・・・・0MSレ
ジスト、91、−7 7・・・・・・加速電圧が20KVの電子ビーム、8・
・・・・・加速電圧が5KVの電子ビーム、9・・・・
・・レジストパターン。 代理人の氏名 弁理士 中 尾 敏 男 ほか1名3−
−−シリコX基紙 q−−−しジスYノ1″′ターン 第  2L                    
     、〜−−列゛ズL2−−−電峯ビーム 3−−−シリコン茅1及 Q= イo” eV/c 6m2 第3図    2=−電)じ″−4 3−−−シリコシ基紘 4−一一正°ジレQスL
FIG. 1 is a cross-sectional view of a resist pattern formed by the electron beam exposure method of the present invention. 3... Silicon substrate, 6... 0MS resist, 91, -7 7... Electron beam with acceleration voltage of 20 KV, 8...
...Electron beam with accelerating voltage of 5KV, 9...
...Resist pattern. Name of agent: Patent attorney Toshio Nakao and 1 other person3-
--Silico
,~---Column size L2---Electric beam 3---Silicone 1 and Q=Io'' eV/c 6m2 Figure 3 2=-Electric)ji''-4 3---Silicoshi base 4 -Ichimasa °Gilet Q-S L

Claims (1)

【特許請求の範囲】[Claims] 半導体基板上に感電子線レジスト膜を塗布した後、前記
感電子線レジスト膜を貫通する加速電圧の電子線を用い
て、所定パターンを前記感電子レジスト膜上に描画する
第1の露光と、前記感電子線レジスト膜を貫通すること
のない加速電圧の電子線を用いて、前記パターンを前記
感電子線レジスト膜上に描画する第2の露光とを有する
ことを特徴とする電子ビーム露光方法。
After applying an electron beam sensitive resist film on a semiconductor substrate, a first exposure of drawing a predetermined pattern on the electron beam sensitive resist film using an electron beam at an accelerating voltage that penetrates the electron beam sensitive resist film; and a second exposure of drawing the pattern on the electron beam-sensitive resist film using an electron beam at an accelerated voltage that does not penetrate the electron beam-sensitive resist film. .
JP17796385A 1985-08-13 1985-08-13 Electron beam exposing method Pending JPS6237930A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17796385A JPS6237930A (en) 1985-08-13 1985-08-13 Electron beam exposing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17796385A JPS6237930A (en) 1985-08-13 1985-08-13 Electron beam exposing method

Publications (1)

Publication Number Publication Date
JPS6237930A true JPS6237930A (en) 1987-02-18

Family

ID=16040136

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17796385A Pending JPS6237930A (en) 1985-08-13 1985-08-13 Electron beam exposing method

Country Status (1)

Country Link
JP (1) JPS6237930A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7588803B2 (en) * 2005-02-01 2009-09-15 Applied Materials, Inc. Multi step ebeam process for modifying dielectric materials

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7588803B2 (en) * 2005-02-01 2009-09-15 Applied Materials, Inc. Multi step ebeam process for modifying dielectric materials

Similar Documents

Publication Publication Date Title
JPH05205989A (en) Lithography method and manufacture of semiconductor device
JPS6237930A (en) Electron beam exposing method
US5186788A (en) Fine pattern forming method
JPH0653106A (en) Formation of fine resist pattern
JPH0360113A (en) Formation of resist pattern for lift-off
JPS5832420A (en) Electron beam lithography
JPS5976428A (en) Formation of fine pattern
JPH0147009B2 (en)
JP2610898B2 (en) Fine pattern forming method
JPS5680130A (en) Manufacture of semiconductor device
KR100208321B1 (en) Pattern forming method
JP2585320B2 (en) Pattern formation method
JP2856593B2 (en) Method of forming resist pattern
JPS59222929A (en) Method for formation of pattern
JPS62144161A (en) Formation of resist pattern
JPS5892223A (en) Resist pattern formation
JPS6112027A (en) Forming method of resist pattern
JPH0313949A (en) Resist pattern forming method
JP2639168B2 (en) Charged beam exposure method
JPH0789532B2 (en) Electronic beam exposure method
JPH06101422B2 (en) Resist pattern formation method
JPS6428821A (en) Fine pattern formation
JPS55158635A (en) Mask
JPS58100428A (en) Formation of pattern
JPH0719061B2 (en) Resist pattern formation method