JPS6235951A - Inter-memory data transfer system - Google Patents

Abstract

PURPOSE:To transfer data between memories directly at a high speed by making an address counter operatable and counting up it with a clock signal while a CPU releases a bus. CONSTITUTION:Though a gate 6 is normally turned on, it is turned off by a transfer control signal C in the high-speed data transfer mode to disconnect a CPU 4 from a system address bus SAB. A gate 7 has a read gate and a write gate, and they are turned off together by the control signal C in the high-speed data transfer mode to disconnect the CPU 4 from a system data bus SDB. An address counter control part 5 has an address counter, and this counter is made unoperated normally; but in the high speed data transfer mode (the CPU released the bus SAB), the counter is made operatable and is counted up by every clock signal from a clock generating part 3 and the address as the output is outputted onto the bus SAB.

Description

[Detailed description of the invention] [Technical field of invention] The present invention relates to a data transfer method between memories.

[Prior Art and Problems] Generally, in the case of program transfer, a CPU transfers data by once reading data from a memory and then writing the data to another memory. However, with this transfer method, it is necessary to execute approximately 10 instructions, which takes a very long time (especially in the case of a large amount of data).

To solve this problem, a direct memory access method using a DMA (direct memory access) controller is used. Although this method enables high-speed transfer, the DMA controller itself requires logic such as a small CPU, so various devices (typically
address register, counter register, control register,
(status registers, etc.), the configuration is complex, and the cost is high.

[Objective of the Invention] Therefore, the present invention provides a transfer method that can transfer large amounts of data between memories with a simple configuration and at high speed (faster than a method using a DMA controller) without using a DMA controller. The purpose is to

[Summary of the Invention] This invention specifies the data sending side memory and the data receiving side memory, and while the CPU releases the bus (system address bus, system data bus), the memory address counter is increment/decrement every l clock signal from a clock generator;
While the memory address counter is outputting the same address to the system address bus -F, the clock signal is used to control the data sending side memory and the data receiving side memory to a data sending enabled state and a data receiving enabled state, respectively. This is a summary of what was done.

[Embodiment] FIG. 1 is a block diagram of the overall configuration of a minimum unit embodiment using the present invention. 1 in the figure is the first memory RA
MI and 2 represent RAM2, which is the second memory. 3
is a clock generator whose output signal, a clock signal, is supplied to the CPU 4 and also to the address counter controller 5.

The bidirectional system data bus Σπ1 connects various devices (
Here, CPU 4, RAMI, RAM 2) are mutually coupled, and similarly, various devices (here CPU, RAM 1, RAM 2, address counter control section 5) are interconnected to system address bus Σ.

Gate 6 is normally conductive, but in the high-speed data transfer mode according to this embodiment, it is turned off by control signal C (transfer control signal), disconnecting CPU 4 from system address bus Σ1. Gate 7 has a read gate and a write gate, both of which are turned off by control signal C under high-speed data transfer mode, disconnecting CPU 4 from system data bus ΣD1. In normal program transfer to the CPU 4, the read gate of gate 7 is closed according to a data read command from the CPU 4 and data is taken into the CPU, and the write gate is closed according to a data write command and data is taken out from the CPU. It is now possible to

The address counter control unit 5 has an address counter, and this counter is normally placed in an inactive state.
In the high-speed data transfer mode (while the CPU releases the system address bus SAB), it is placed in an operational state and is incremented by each clock signal from the clock generator 3, and the output address is transferred to the system address bus. It is set to be displayed on Gym 1.

8(i) represents a control converter for the first memory, and in the figure, the memory control converter 8(1) is used for the RAMI which is the first memory, and the memory control converter 8(1) is used for the RAM which is the second memory.
A memory control converter 8(2) is shown for I. Each memory control converter is configured to supply necessary control signals to the associated memory according to the states of various control signals sent from the CPU 4 via the control bus.

For convenience of explanation, control signals used in the embodiment are listed below, and their meanings will be briefly explained.

C: Data transfer control signal. A signal supplied from the CPU 4 to the gate 6.7 turns off the gate during the data transfer mode and disconnects the CPU from SAB and SDB.

cs(i): first memory selection signal. For example, C3I
is a selection signal for RAMI, which is the first memory.

This signal is used for normal program transfer (normal mode) of the CPU, and becomes active at low level "L" (the same applies to other control signals).

The data is supplied from the CPU 4 to the first memory control converter 8(i).

RD: Read signal. Used in normal CPU mode.

The data is supplied from the CPU 4 to various memory control converters.

WR Nilight signal. The following is the same as HD.

CLK: Clock generated by the clock generator 3. CPU
4, is supplied to the address counter control section 5 and the memory control conversion section.

DMARQ: Direct memory access (high speed data transfer) request signal. It is supplied from the CPU 4 to the address counter control section 5.

BUSRQ: Bus release request signal. A signal supplied by the address counter control unit 5 to the CPU 4 in response to DMARQ.

BUSAK: Bus release signal. A signal that the CPU supplies to the address counter control unit 5 and all memory control units when the bus SAB and the bottom are released.

RDS (i): Read selection signal supplied from the CPU to the first memory control converter. Used in high speed data transfer mode.

WR3(i): Write selection signal supplied from the CPU to the first memory control converter. The following is the same as RDS (i).

MRD (i): First memory read signal. Supplied by the associated memory control converter.

MWR(i): first memory write signal. The following is M
Same as RD(i).

Mcs (i): Chip selection signal of the first memory. The following is the same as MRD(i).

The memory control converter 8(i) has logic as shown in the table below.

For example, in the normal mode, the memory write signal MRDI of the first memory, RAM1, is controlled by the read signal RD (MRD 1=RD), and in the high-speed data transfer mode, the RDSI signal is 'L''. (MRDl=CLK), otherwise °゛H'
becomes. The following is omitted.

FIG. 2 shows an example of the configuration of a memory control converter that implements the logic described in item 1. Since the configurations of the games 18-1 to 8-14 are obvious from the illustration, the explanation will be kept brief. In this example, the BUSAK signal is used as a signal indicating that the high-speed data transfer execution mode is in progress. The inverter 8-2 provided on the BUSAK line 2 acts to inhibit the RD double signal WR double signal (signal used in normal mode) during data transfer at gates 8-1 and 8-6. -1 and 8-6 are enabled. In addition, various gates are selectively enabled/disabled by the BUSAK signal) 21. ”l-
However, such an enable/disable means is not necessarily provided on the memory control converter side, but can be realized by hardware and/or a program on the CPU side. For example, the RD and WR double signals are fixed to "H" during high-speed data transfer, and the RDS
(i), WR3 (i) If the CPU side sets the signal to be fixed at H11 in the normal mode, it can be realized with a simpler configuration than that shown in FIG. An example thereof is shown in FIG. In this example, the MC in high-speed data transfer mode
3(i) becomes “L” (not CLK) when WR3(i) or WR3(i) is “L” (MCS (i
)=WRS (i) RDS(i), therefore W
σ Ding's sword = WR Ding] sword URD S (i)).

Next, the operation of high-speed data transfer by the apparatus shown in FIGS. 1 and 2 will be explained with reference to FIGS. 3 and 4.

For convenience of explanation, the first memory is
A case will be described in which data is transferred to RAMI, which is the memory of the computer.

First, use RAM2 as the reading side memory (data sending side memory).
(step 101) This allows RDS2
The signal is fixed at "L" and is supplied to the RAM 2 (see FIG. 2). Note that the WRS2 signal remains at "H". RAMI is also selected as the writing side memory (data receiving side memory) (step 102). As a result, the WRDI signal is fixed at "L"(RDSl="H"). Next, CPU 4 requests DMA (step 103). As a result, a DMARQ signal (high-speed data transfer request signal) is sent to the address counter control section 5. In response to this, the address counter control unit 5 resends BUSRQ ( ) request signal) to the CPU side. Therefore, the CPU checks in step 104 whether or not there is a bus request, and if there is no bus request, it processes as an error 105. If there is a bus request, CP
U executes the command for bus disconnection (step 10
6).

As a result, a transport control signal C is generated to turn off gates 6 and 7, and the CPU is separated from the system address bus SAB and system data bus SDB. Next, the CPU outputs BUSAK (bus release signal) (step 107).

By supplying this signal BUSAK, the address counter of the address counter control unit 5 is enabled, counts up every l clock signal (falling edge) from the clock generator 3, and sends the address, which is the count output, to the system address bus Σ. Output on 1. On the other hand, BUSA
The K signal is also supplied to each memory control converter, and in the control converter 8(2) for the second memory (RAM2), the RD
S2 signal "L" passes through gate 8-3 and enables gate 8-4. Therefore, the clock signal from the clock generator passes through this gate 8-4 and further passes through the gate 8-5 and is supplied to the RAM2 as a memory read signal MRD2. Similarly, the chip selection signal MC3 is also controlled by the clock signal and is sent to the RAM2. chip is enabled, and the RAM 2 is controlled to be in a data transmittable state (data read state). Further, in the control conversion unit 8(1) for the first memory (RAMI), the WR3I signal "L" passes through the gate 8-7 and enables the gate 8-8.

Therefore, the clock signal passes through this gate 8-8 and further passes through gate 8-9 and is supplied to RAMI as a memory write signal MWRI. Furthermore, this clock signal passes through gates 8-10.8-13.8-14 and becomes a memory selection signal MC5I, which chip-enables RAMI.

As a result, RAMI is controlled to be in a data receivable state (data write state).

In this way, the address counter is incremented for each clock signal from the clock generator, and while the address counter holds the same address, RAM2, which is the memory on the data transmitting side, becomes ready for data transmission. Since RAMI, which is the data receiving side memory, is ready to receive data, the RA specified by the above address
Data is output from the memory location in M2 and transferred directly to the memory location in RAMI specified by the same address (
(see FIG. 4), one memory word (one byte in the case of an 8-bit memory) is transferred every clock, so data is transferred at the highest speed. This state is indicated by step 108.

Although FIG. 4 only shows two data transfers in order to simplify the drawing, in reality, data transfer continues until the address counter of the address counter control section is reset.

Now, when the address counter is reset (data transfer completed), the address counter control section releases the BUSRQ signal (step 109).
Step tio) to release SAK (bus release signal)
, the data transfer signal C is withdrawn to release the off state of the gate 6.7, and the connection between the CPU and the bus 181 and S08 is restored (step 111). Furthermore, the CPU is MDAR
Cancel the Q (direct data transfer request) signal (step 112) and release RDS2 and WRSI (return to “H”)
(step 113). In this way, normal operation is restored.

As can be seen from FIG. 2, in the normal program transfer mode of the CPU, the memory read signal MRD(i) is controlled by the read signal RD, and the memory write signal MWR(i) is controlled by the read signal RD.
i) is controlled by the write signal WR, and the memory selection signal MC5(i) is controlled by the selection signal 03(i).

When performing high-speed, direct data transfer from RAMI to RAM2, it is sufficient to perform the opposite procedure to the case of transfer from RAM2 to RAMI. For example, in step 101, RDS2
Instead, RDSI is set to "L" to designate RAMI as the data transmission side memory. In step 102, WR32 is set to "L11" instead of WR5I to designate RAM2 as the data receiving memory, and so on.

Note that in the embodiment described in section 1, RAMI is used as the first memory and RAM2 is used as the second memory, but the present invention is not limited to this, and for example, a ROM may be used as the first memory. In the case of ROM, the memory read signal MRD and memory write signal MWR are usually unnecessary (not used), so
In the configuration shown in FIG. 2, the circuit for generating MRD(i) and MWR(+) may not be provided.

Furthermore, a third memory, a fourth memory, etc. can be freely added as memories to which data should be directly transferred. That is, it is sufficient to add a memory control converter for the additional memory and to enable the CPU to supply the necessary control signals thereto.

Further, the address counter control section 5 can have various configurations, but the simplest configuration can be realized by practically using only an address counter.

For example, use the DMARQ signal (or equivalent control signal) to reset (or preset) the address counter.
signal, remove the BUSRQ signal, and use the BUSA
The K signal (or an equivalent control signal) is used as an enable signal for the address counter, and while the BUSAK signal is output, the address counter is incremented by the clock signal from the clock generator 3, and the address counter is incremented by the clock signal from the clock generator 3. The BUSAK signal may be canceled by supplying a carry output to the CPU side.

Furthermore, various changes can be made to the control signals supplied from the CPU to the memory control converter. In the illustrated embodiment, by using the read select signal RDS(j) and the write select signal WR5(i), it is possible to simultaneously select the memory to be used in the high-speed data transfer mode and specify the write (or read) of the memory to be used. Is going.

In other words, one signal specifies the memory on the data receiving side, and another signal specifies the memory on the data transmitting side, but the present invention is not limited to this.
For example, by using a signal to select the memory to be used in direct data transfer and a signal to specify that the memory to be used is on the read side, a signal to specify that the memory to be used is on the write side (in other words, read select The data transmitting side memory or the data receiving side memory may be specified (the signal is divided into a read signal and a select signal, and the write select signal is divided into a write signal and a select signal and output from the CPU). Changes to the CPU and program necessary for this purpose, as well as changes to the memory control section, can be made within the range obvious to those skilled in the art.

Furthermore, in the embodiment, RAM1. As RAM2.

A type of memory that uses the read signal and write signal as separate signals (memory with separate read input terminal and write input terminal) is used, but only one read/write input terminal (usually marked ηV) is used. , ``H'', ``L''
[Effect of the invention] As is clear from the above explanation, in this invention, the CPU
While the bus ΣAB and SDR are released, the address counter is enabled so that it can be incremented by the clock signal, and its count output, that is, the address, is outputted onto the system address bus. Then, while the same address is held on the system address bus, the data transmission memory and the data reception memory are controlled to the data transmission state and data reception state, respectively, using the clock signal. Therefore, one memory word is transferred between memories every l clocks output by the clock generator. In other words, there are devices that allow large amounts of data to be transferred between memories at the highest speeds. Moreover, it does not use anything like a conventional DMA controller and enables high-speed data transfer with a simple configuration, which is highly effective.

It is particularly suitable for transferring data between ROM+RAM, RAM MRAM, and RAM card eRAM.

[Brief explanation of drawings]

Figure 1 is a configuration block diagram of a minimum unit embodiment using this invention, Figure 2 is a circuit diagram showing an example configuration of the memory control converter shown in Figure 1, and Figure 3 is high-speed data transfer from RAM2 to RAMI. Flowchart for performing this, Figure 4 shows RAM2
FIG. 5 is a circuit diagram showing a second configuration example of the memory control converter shown in FIG. 1. l,? ...RAM, 3 ... Clock generation section, 4 ... CPU, 5 ... Address counter control section, SAB ... System address bus , SDB...System data bus, 8 (1
), 8(2)...Memory control conversion unit, 6.7.
・Gate Club. Figure 2

Claims (1)

[Scope of Claims] Means for specifying a data sending side memory and a data receiving side memory; a memory address counter; a clock generator; a disconnecting means for disconnecting a CPU from a system address bus and a system data bus; means for incrementing the memory address counter for each clock signal from the clock generator under the condition that the memory address counter is disconnected from the bus by means; and while the memory address counter holds the same address under the condition; and means for controlling a data transmitting side memory and a data receiving side memory to a data transmitting state and a data receiving state, respectively, using a clock signal from the clock generator.