JPS6235951A - Inter-memory data transfer system - Google Patents

Inter-memory data transfer system

Info

Publication number
JPS6235951A
JPS6235951A JP17549685A JP17549685A JPS6235951A JP S6235951 A JPS6235951 A JP S6235951A JP 17549685 A JP17549685 A JP 17549685A JP 17549685 A JP17549685 A JP 17549685A JP S6235951 A JPS6235951 A JP S6235951A
Authority
JP
Japan
Prior art keywords
bus
data transfer
cpu
gate
counter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17549685A
Other languages
Japanese (ja)
Inventor
Masato Soshi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Casio Computer Co Ltd
Original Assignee
Casio Computer Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Priority to JP17549685A priority Critical patent/JPS6235951A/en
Publication of JPS6235951A publication Critical patent/JPS6235951A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To transfer data between memories directly at a high speed by making an address counter operatable and counting up it with a clock signal while a CPU releases a bus.
CONSTITUTION: Though a gate 6 is normally turned on, it is turned off by a transfer control signal C in the high-speed data transfer mode to disconnect a CPU 4 from a system address bus SAB. A gate 7 has a read gate and a write gate, and they are turned off together by the control signal C in the high-speed data transfer mode to disconnect the CPU 4 from a system data bus SDB. An address counter control part 5 has an address counter, and this counter is made unoperated normally; but in the high speed data transfer mode (the CPU released the bus SAB), the counter is made operatable and is counted up by every clock signal from a clock generating part 3 and the address as the output is outputted onto the bus SAB.
COPYRIGHT: (C)1987,JPO&Japio
JP17549685A 1985-08-09 1985-08-09 Inter-memory data transfer system Pending JPS6235951A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17549685A JPS6235951A (en) 1985-08-09 1985-08-09 Inter-memory data transfer system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17549685A JPS6235951A (en) 1985-08-09 1985-08-09 Inter-memory data transfer system

Publications (1)

Publication Number Publication Date
JPS6235951A true JPS6235951A (en) 1987-02-16

Family

ID=15997055

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17549685A Pending JPS6235951A (en) 1985-08-09 1985-08-09 Inter-memory data transfer system

Country Status (1)

Country Link
JP (1) JPS6235951A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07281917A (en) * 1994-04-13 1995-10-27 Nec Corp Cpu switchin circuit

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5441631A (en) * 1977-09-09 1979-04-03 Casio Comput Co Ltd Fixed program set system for control
JPS60120457A (en) * 1983-12-05 1985-06-27 Toshiba Corp Controller of direct memory access

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5441631A (en) * 1977-09-09 1979-04-03 Casio Comput Co Ltd Fixed program set system for control
JPS60120457A (en) * 1983-12-05 1985-06-27 Toshiba Corp Controller of direct memory access

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07281917A (en) * 1994-04-13 1995-10-27 Nec Corp Cpu switchin circuit

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