JPS6232556B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data processing system having a stack structure.

In the prior art, the stack structure is typically defined by software. When data in the stack is accessed under hardware control, it is accessed according to the stack pointer that holds the address of the last data stored on the stack.

When data is to be stored on the stack, the stack pointer is first decremented by the size of the data, and the store operation is performed to this decremented address. Further, when data is taken out from the stack, the data is taken out from the address indicated by the stack pointer, and then the value of the stack pointer is increased by the size of the data taken out.

In such a configuration, by constantly checking the value of the stack pointer using a software command, too much data is stored on the stack, and the data overflows into storage areas other than the stack area, resulting in overflow of the storage area. Destruction of the contents shall be prevented.

In addition, it is necessary to perform a check in software to issue a warning when attempting to retrieve data from a stack that is already empty due to a mistake in program logic.

The purpose of the present invention is to prevent data overflowing the stack area from destroying other main memory areas, and to speed up the detection of errors in software logic by using hardware without using additional software instructions. The object of the present invention is to provide a data processing system that can be executed.

The system of the present invention comprises: address holding means for holding a storage location in main memory of a last-in-first-out data structure; and at least one storage location for holding the number of words used to date of said data structure. , at least one storage location for holding the maximum capacity of said data structure and at least one storage location for each data frame for dividing said data structure into one or more data frames and holding the size of each data frame. storage means having a location, and calculation for calculating the starting address of the most recently acquired data frame based on the contents of the address holding means and the contents of a storage location holding the number of words used in the data structure. means for updating the number of used words in the data structure and the number of words of the most recent data frame, activated in response to a machine instruction manipulating the data structure, based on the contents of the operation code of the machine instruction; an updating means, when storing data in the data structure, compares the number of words used so far in the data structure with the maximum capacity of the stack, and when the former exceeds the latter due to the storage operation; A means for instructing software to interrupt the execution of an instruction currently being executed, and a method for comparing the number of words of the newest data frame with the number of words of the data to be retrieved when retrieving data using the data structure. and means for generating the determination in the software when the latter is large.

Next, the present invention will be explained in detail with reference to the drawings.

Referring to FIG. 1, the stack structure used in the present invention includes an address register 1 that is included in the central processing unit and holds the address of the stack data structure, and a stack that is specified by the address register Area 2 of the main memory stores the number of words of data stored in the area, that is, the number of words indicated by 5, and a location corresponding to the maximum capacity of the stack area, that is, the number of words indicated by 6, is stored in a location that is one address larger than area 2. An area 3 for holding the number of words holds the number of words contained in the last acquired data frame 7 at the address obtained by subtracting the contents of the area 2 from the contents of the address register 1, that is, the number of words corresponding to 8 in FIG. It has Area 4.

This stack is first-in-last.
Execute out data retrieval operation.

Instructions for manipulating the stack are divided into those for changing the framework of the stack and those for manipulating data in the stack as normal instructions.

The former instruction requires a load T register
LDT, store T register STT, acquire stack frame ACQ, link stock stack frame RLQ, modify
Contains 5 frame range MFL instructions. Here, the T register is a register that stores an address indicating the location of the oldest data stored on the stack.

The Load T Register LDT instruction is an instruction that selects one of the address registers that can be operated by software and loads the contents of that register into the address register 1 in the central processing unit shown in FIG.

This instruction changes the stack structure in main memory to
It acts as a link to the registers in the central processing unit.

The store T register STT instruction, on the other hand,
The contents of address register 1 shown in the figure are stored in a predetermined address register.

The Acquire Stack Frame ACQ instruction is an instruction that creates a new data frame in the stack. The size of this data frame is given by the instruction. By executing the ACQUIRE STACK FRAME ACQ command, the contents of area 2 indicating the number of words used so far in the stack are increased by the size of the created data frame +1. The behavior of the relink issue RLQ command is Acquire ACQ.
It works in the opposite direction to that of the command. This command releases the area of the last created data frame in the stack.

The Modify Frame Resin MFL instruction is an instruction that increases or decreases the size of the last data frame created in the stack by the amount specified by the instruction.

Next, a case will be described in which data in the stack is manipulated using normal instructions.

A normal instruction is an instruction that takes an operand in main memory into a register of a central processing unit (load instruction) or stores the contents of a register in main memory (store instruction).

If the field specifying the address of an operand in an instruction indicates an operation on the stack,
The operation is as follows. In addition, in this example,
Regarding the case where data is stored in a stack provided in the main memory in the direction in which the addresses of the main memory decrease, while data is retrieved from the stack in the direction in which the addresses in the main memory increase. As will be explained, it is easy to change so that data is stored in the stack in the direction of increasing main memory addresses, and data is retrieved from the stack in the direction of decreasing main memory addresses.

When an instruction stores data in the stack, the central processing unit subtracts the number of words currently used in the stack stored in area 2 from the contents of address register 1 shown in FIG. obtain. The address indicating this area 4 is 1
By incrementing by 0, the address 9 of the latest data in the stack can be created.

To push the contents of a register onto the stack, address 9 is first reduced by the size of the data being pushed. This secures an area for storing data.
Next, increase the size of the operand that stores the size of the latest data frame written in area 4, and set the address where the operand is written by -1.
stored at the specified address. Furthermore, the number of words used so far in the stack written in area 2 is increased by the size of the operand, and
Write back to the location. Next, compare the content written back to area 2 with the maximum capacity of the stack written to area 3, and if the former is larger than the latter,
Generate indexing. This indexing means that a certain instruction in a certain program interrupts the execution of another instruction in the same program and causes the certain instruction to be executed.

When an instruction retrieves data from the stack, the address 9 of the latest data is obtained in the same way as when storing data. Extract data equal to the size of the operand from address 9. At this time area 4
The size of the latest data frame written in is compared with the size of the operand, and if the latter is larger than the former, an error occurs in the software logic and an index is generated.

Next, the size of the retrieved operand is reduced from the contents of area 4, and this value is written to the address of area 4 plus the size of the operand.

Furthermore, the contents of area 2 are reduced by the size of the operand.

Referring to FIG. 2, one embodiment of the present invention is comprised of a main storage device 10, an intermediate processing device 12, and a bus 11 connecting these devices. The central processing unit 12 includes a buffer 13 and a register 1.
4, instruction register 15, address register 16,
a decoder 17 for decoding the instructions in the instruction register 15; a register file 18 having a T register 19 for holding the address of the stack data structure;
a numerical logic operation unit 20 that operates on data from the register 14 or register file 18; a control store 21 that reads out microinstructions based on the start address from the decoder 17;
and a decoder 22 that decodes microinstructions from the control store 21.

Next, the operation of this embodiment will be explained in detail with reference to FIGS. 2 and 3. First, the main memory 10
Retrieve the command from. For this purpose, the address of the instruction stored in the main memory 10 is set in the address register 16.

Next, a read start signal is given according to the instruction of the microinstruction. Instructions read from main memory 10 are stored in instruction register 15. The address of the instruction stored in the register 15 is stored in the main memory 1.
If a stack area of 0 is not indicated, the instruction is executed. If the instruction is
When a stack area of 0 is not indicated, the address of T register 19 is set to unit 20 and line 2.
5 and stored in the address register 16.
Next, the address of the register 16 is given to the main memory 10 via the bus 11, and the count word is read from the location corresponding to area 2 in FIG. 1 of the main memory 10 specified by the address. 11 and stored in the register 14. The count word stored in register 14 is transferred to bus 23,
unit 20 and is stored in working register WRI of register file 18 via line 25. Next, the address stored in the address register 16 is incremented by 1, and the incremented address is bus 1.
1 to the main storage device 10. In response to this address, word MW is read from area 3 of main memory 1 shown in FIG.
The data is stored in the register 14 via the . register 1
The word MW stored in register file 1 is transferred via bus 23, unit 20, and line 25 to register file 1.
8 working register WR2. Next, the count word stored in working register WR1 of register file 18 is subtracted from the address stored in T register 19 by unit 20, and the result of the subtraction is sent to address register 1 via line 25.
6 and register file 18.
is stored in working register WR4.

Next, the address set in address register 16 is applied to main memory 10 via bus 11 to designate area 4 of device 10. In response to this instruction, data FL is sent to register 1 via bus 11.
After being set to 4, bus 23, unit 20,
It is set in working register WR3 of register file 18 via line 25.

When the instruction stored in the instruction register 15 instructs an operation (PUSH) to push the contents of the register onto the stack of the main memory 10, the constant given from the decoder 17 is determined from the contents of the working register WR4 of the register file 18. unit 20, and the subtraction result is sent to working register WR0 of register file 18 via line 25.
will be written to.

From the next written contents of register WR0,
The constant 1 given from the decoder 17 is subtracted by the unit 20 and the result of the subtraction is stored in the address register 16 via the line 25. Next, the operand size given from the decoder 17 is added to the working register WR3 of the register file 18 in the unit 20, and the addition result is stored in the buffer 13 via the line 25.

Next, the operand size from the decoder 17 is added to the count word CW of the working register WR1 in the unit 20, the contents of the working register WR2 are subtracted from the addition result in the unit 20, and the carry signal is sent to the unit 20.
You can check whether or not to output from. If the carry signal is output, the currently executing software instruction is interrupted and a new instruction is executed. If the carry signal is not output, the contents of T register 19 are stored in register 16 via unit 20 and line 25. Next, the operand size from the decoder 17 is added to the contents of the working register WR1 in the unit 20, and the addition result is stored in the main memory 10 via the buffer 13 and the bus 11.

When the instruction stored in the instruction register 15 does not instruct an operation (PUSH) to push the contents of the register onto the stack of the main memory 10, the address of the address register 16 is incremented by one. This +
Main memory device 2 indicated by the address specified by 1
Operands are read from area 7 shown in FIG. 1 and set in register 14 via bus 11. The operands set in this register 14 are connected to bus 23, unit 20, and line 25.
The data is stored in the working register W0 of the register file 18 via the register file 18. Next, register file 1
The operand size from the decoder 17 is subtracted from the contents of working register WR3 of No. 8 in unit 20, and the result of the subtraction is shown on line 25 and buffer 1.
3 and the bus 11, the data is stored in the area 4 shown in FIG. 1 of the main storage device 10.

Next, the operand size from the decoder 17 is subtracted from the contents of the working register WR3 in the unit 20, and it is checked whether or not a carry signal is output from the unit 20. If the carry signal is not output, the software command is interrupted and a new command is executed. If a carry signal is output, the contents of T register 19 are set in register 16 via unit 20 and line 25. Next, working register 19
, the operand size from the decoder 17 is subtracted in unit 20, and the result of the subtraction is shown on line 25,
The data is written via buffer 13 and bus 11 to area 2 shown in FIG. 1 of main memory 10.

The present invention has the advantage that data in main memory can be easily protected when accessing data in the stack.

[Brief explanation of the drawing]

Figure 1 is a diagram showing the stack structure of the present invention, Figure 2 is a diagram showing the stack structure of the present invention.
The figure shows an embodiment of the present invention, and FIG. 3 is a diagram for explaining the operation of the embodiment shown in FIG. In Figures 1 to 3, 1... pointer register for the stack structure, 2... the number of words used in the stack up to now, 3... the maximum capacity of the stack area, 4... the number of words in the frame, 5... the number of words in the stack. Showing the size, 6... Showing the size of 3,
7...data frame, 8...indicating the size of 4, 9...pointer pointing to the latest data in the stack, 10...main memory, 11...common bus,
12...Central processing unit, 13...Data buffer,
14...Memory data register, 15...Instruction register, 16...Memory address register, 17
...Instruction decoder, 18...Register file,
19... Stack pointer, 20... Numerical logic operation unit, 21... Control store, 22
...Microinstruction decoder, 23...ALU input bus A, 24...ALU input bus B, 25...
ALU output bus.

Claims (1)

[Scope of Claims] 1. Address holding means for holding a memory location in main memory of a last-in, first-out data structure; and at least one memory for holding the number of words used to date of the data structure. at least one storage location for holding the maximum capacity of said data structure; and at least one storage location for each data frame for dividing said data structure into one or more data frames and holding the size of each data frame. a storage means having a storage location; and calculating a starting address of the most recently acquired data frame based on the contents of the address holding means and the contents of the storage place holding the number of words used in the data structure. computing means activated in response to a machine instruction manipulating the data structure and calculating the number of used words in the data structure and the most recent data frame based on the contents of the operation code of the machine instruction; an updating means for updating the number of words; and when storing data in the data structure, the sum of the number of words used up to now in the data structure and the number of words of the data frame to be stored is added to the data structure. When the maximum capacity of the data structure is exceeded, the software is configured to issue an instruction to interrupt the execution of the currently executing instruction to prevent the storage of the data to be stored; A data processing system comprising means for comparing the number of words of a new data frame with the number of words of data to be retrieved and causing the software to make the determination when the latter is larger.