JPS6229930B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an encoding device for a cyclic code, which is one of the error correction codes, and is particularly suitable for encoding in a burst mode transmission system.

In order to correct errors in the transmitted data bits, the transmitting side adds a check bit string to the information bit string and transmits it, and the receiving side decodes it based on its redundancy to correct the bit errors. A method of detecting and correcting is adopted. For example, September 1972
In IEICE communication system research group material CS77-66 (IEICE Technical Report Vol.77 No.105) published on April 1st, BCH code, which is a type of cyclic code, is applied to PCM-TDMA satellite communication line. It is stated that the aim is to improve communication quality. according to this,
When encoding and decoding signal sequences transmitted and received in bursts as in the TDMA communication system, it is advantageous to complete the encoding and decoding in each burst unit. In this case, unless the burst length is divisible by the block length, special operations are required to complete encoding and decoding at the end of the burst.

Conventional cyclic encoding devices that operate in burst mode include a method that adds dummy bits to information bits and encodes the burst length to match an integral multiple of the block length, and a method that adds dummy bits to the information bits so that the burst length matches an integral multiple of the block length. There was a system configuration in which two encoders were used for encoding: one encoder inputs and encodes information bits shorter than the normal block length, and the other encoder inputs and encodes information bits shorter than the regular block length. However, the former method has low information transmission efficiency, and the latter method has drawbacks such as being complex, large-scale, and expensive. As a measure to eliminate this drawback, the above-mentioned document suggests that idea by writing from the end of page 6 to the beginning of page 7 that ``a method that does not actually send out dummy bits is conceivable.'' , does not explain anything further.

Therefore, the first object of the present invention is to perform not only normal cyclic encoding but also shortened encoding in which the number of information bits is less than one block length in order to perform error correction encoding in burst mode. The object of the present invention is to realize an encoding device that can perform encoding using the same encoder.

A second object of the present invention is to provide an efficient encoding device with a simple configuration.

According to the present invention, a test bit generation circuit generates a test bit string upon receiving an input information bit string;
An encoding device comprising: a switching circuit that adds the generated check bit to the end of the input information bit string and outputs it as a cyclic code; and a timing control circuit that controls the timing of these two circuits using a control signal. The timing control circuit detects when the number of bits of the input information bit string reaches the number of information bits of one block of the cyclic code, and when the number of bits is less than the number of information bits of one block of the cyclic code. The control signal is configured to generate a control signal that completes the operation of the test bit generation circuit and outputs the output of the test bit generation circuit after the information bit when the last data bit is input. As a result, if the number of bits in the input information bit string is less than the normal number of bits, "0" is assumed to precede the "0" bit by the number of missing information bits. A cyclic code encoding device is obtained which is characterized by encoding without insertion.

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, and FIG. 2 is a time chart showing the operation of the embodiment of FIG. The explanation will be given below using both figures together. Each block of input signal a input from information input terminal 1 consists of a total of n bits, the first k bits are information bits, and the remaining n−k bits are test bits to be formed later. Indicates a blank area where bits should be placed. However, the last block on the far right in Fig. 2 is an information bit sequence in which the number of information bits k' caused by the burst length not being divisible by the block length is less than the normal value, that is, when k' is smaller than k. It shows. Timing set signal b input from timing input terminal 2
are pulse signals p ₁ , p ₂ , . . . _{p n} indicating the timing of the last information bit in each of the above blocks. I'm a minute early. When the timing control circuit 3 receives the above-mentioned timing set signal b, the output, that is, the control signal C, which was "H" until then becomes "L", and when it counts n-k (corresponding to the above-mentioned blank space) in bits, This counter returns to "H" again. The check bit generation circuit 4 is a circuit that regards the input information bit string as a polynomial, divides it by a code generation polynomial, and outputs the remainder. It consists of a back shift register.

When the input information bit string a is input while the timing control circuit output C is in the "H" state, the AND circuits 5 and 6 are opened, and the AND circuit 7 is closed because it is an inversion circuit 8. Therefore, on the one hand, the input information bit string a is output via the OR circuit 9, and on the other hand, the test bit generation circuit 4
The output of the exclusive OR circuit 10 which receives the output d and the input information bit string a as both inputs is received as a feedback value, and division is performed using this, but the output d is blocked by the AND circuit 7 and sent to the encoding device. It is not output to the output terminal 11. The above state continues for k bits. If this period is defined as the first stage, then in the first stage of the output e, the input information bit string a is output as is.

Next, when the input information bit string a ends and the pulse _p1 of the timing set signal b is input, the timing control circuit output c becomes "L" and the AND circuit 5
and 6 are closed, and the AND circuit 7 is opened.
Therefore, the input information bit string a is not output to the output terminal 11, and on the other hand, the test bit generation circuit 4 stops the division operation when the feedback value becomes "0", and outputs the generated and stored test bits. are sequentially outputted via the AND circuit 7 and outputted via the OR circuit 9. The above states are expressed in number of bits as n-
It continues for k times, that is, a blank part of the input signal. Assuming that this period is the second stage, the second stage of the output e is the output of the check bit string of the output d. Therefore, the encoded outputs e of the first and second stages appear successively as an input information bit string and a check bit string as shown in the time chart, and the encoding operation for the first block is completed.

When the above-mentioned second stage is completed, the timing control circuit output c becomes "H", and at the same time, the information bit string is input and the operation for the next block is started, and thereafter each operation of the above-mentioned first stage and second stage is performed. Repeated for each block. Thus, a cyclic code as shown in FIG. 2e is obtained. However, it should be noted that in the mth block of the last burst, the number of information bits is smaller than that of the previous regular one, so the mth pulse p _n of the timing set signal is changed accordingly. It was shipped relatively quickly.

The difference between the cyclic code obtained in this way and the cyclic code obtained by a conventional device that uses only one encoder for encoding information bits of a regular block length is that the length of the last block is The overall required operating time can be saved by the shortened amount, and it is now possible to encode in burst mode without reducing information transmission efficiency due to the addition of dummy bits. This is not only normal cyclic encoding, but also uses a timing set signal b synchronized with the input data for input data with fewer information bits than the regular number of information bits in one block. This is because the timing of transition to the next stage can be accelerated. Note that this timing set signal b may be a pulse p ₁ , p ₂ . . . p _n indicating the last input information bit of each block, or a pulse indicating the beginning and end of a burst.
It may be q ₁ or q ₂ . However, in this case, the timing control circuit 3 is a 1/n counter that starts counting at the pulse of q ₁ and stops counting at the pulse of q ₂ . In any case, the timing control circuit output c may be any control signal that can distinguish between the data part and the check bit part of the input information bit string.

In addition, in the above device of the present invention, in order to consider whether shortening the first stage in the final block will have an unfavorable effect on the operating characteristics of the device, in reality, it is as follows. It can be said that there are no such cases. In other words, the shift register of the divider in the test bit generation circuit 4 starts the division operation from a state where all values are "0", but as long as the input to the divider is "0" from the beginning, the contents of the shift register will not change. Therefore, it can be considered that short input data is actually preceded by a "0" corresponding to the lack of information bits. For this reason, if the division operation is stopped when short data has been input, the same check bits will be generated as when the data is preceded by "0", which is the missing information bit.

As explained above, according to the present invention, by simply controlling the encoding timing, not only the encoding of the regular block length but also the encoding of the shortened code can be easily and efficiently performed, especially for TDMA communication. This method is suitable for coding in systems that transmit data in burst mode, such as the system.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, and FIG. 2 is a time chart showing the operation of the apparatus shown in FIG. Explanation of symbols: 3 is a timing control circuit, 4 is a test bit generation circuit, 5, 6, 7 is an AND circuit, 9
1 is an OR circuit, 10 is an exclusive OR circuit, 5 to 10 of the above are switching circuits, a is an input signal, b is a timing set signal, c is a control signal, d is a test bit string output, and e is a Each represents a cyclic code output.

Claims (1)

[Claims] 1. A check bit generation circuit that generates a check bit string upon receiving an input information bit string, a switching circuit that adds the generated check bit to the end of the input information bit string and outputs it as a cyclic code, and these two circuits. In the encoding device having a timing control circuit that controls the timing of the input information bit sequence using a control signal, the timing control circuit detects when the number of bits of the input information bit string reaches the number of information bits of one block of the cyclic code. In,
If the number of bits is less than the number of information bits for one block of the cyclic code, the operation of the check bit generation circuit is completed at the time when the last data bit is input, and the check bits are generated immediately after the information bit. It is configured to generate a control signal that adds the output of the generating circuit and outputs it, so that if the number of bits in the input information bit string is less than the regular number of bits, the number of information bits that are missing is changed. A cyclic code encoding device characterized in that encoding is performed without inserting a “0” on the assumption that a “0” bit is leading.