JPS62294320A - Logic circuit - Google Patents

Abstract

PURPOSE:To attain the timing control with high accuracy in response to the request for the high speed operation by constituting a delay circuit of a resistive component arranged between an output of a pre-stage gate and an input of a post-stage gate and a capacitive component of the post-stage gate so as to control the timing between an input signal and an output signal. CONSTITUTION:Since RC transient phenomenon takes place by the resistive component arranged between the output of the pre-stage gate and the input of the post-stage gate and the capacitive component of the post-stage gate, a delay time larger than a delay time gammapd specific to the pre-stage and the post-stage gates is obtained. In forming, e.g., the resistive component as a variable component, the delay time is varied optionally. That is, as the resistive component, the resistive comonent of a transfer gate 1 arranged between the pre-stage gate and the post-stage gate 2 is used and the resistive component of the transfer gate 1 is formed as a variable component. Thus, a desired delay time is formed and the timing control with high accuracy is attained.

Description

Detailed Description of the Invention 3. Detailed Description of the Invention A. Field of Industrial Application The present invention relates to a logic circuit for controlling the timing of input signals and output signals, and in particular to a logic circuit such as a G a A 5-IC. The present invention relates to a logic circuit suitable for application to a circuit that performs high-speed processing.

B0 Summary of the Invention The present invention provides a logic circuit that controls the timing of an input signal and an output signal, in which a resistor component disposed between the output of a front-stage gate and an input of a rear-stage gate and a capacitance component of the rear-stage gate as described in -. By configuring a delay circuit according to the following, highly accurate timing tllll?I11 can be realized.

C1 Prior Art In general, a logic circuit constituted by an inverter circuit or the like is sometimes used for signal timing control.

FIG. 3 shows a conventional example of a BFL circuit (Buffered FLIT) that functions as an inverter circuit.
It is a circuit in which two stages of FETs (1o8ic) are connected in series, and
(Field effect transistor) 31, 32, 33, 34 and diode 35 constitute the 1”!
' 37, 38, 39, 41 and a diode 40 constitute a subsequent BFL circuit.

As shown in FIG. 4, the logic circuit having such a circuit configuration has an input 4j' which is a rectangular wave signal;
If l' is 11 degrees and the delay time per stage is τ94, a delay of approximately 2τ94 will occur.

D0 Problems that the invention aims to solve In conventional circuits like this, in order to control the timing of each signal at the design stage, its operation is usually confirmed through simulation, and if necessary, a new inverter circuit is added. We are trying to adjust the timing.

However, in actually manufactured circuits, it is not always possible to obtain elements that meet the designed values due to process problems and the like, and timing deviations may occur. Furthermore, depending on the added inverter circuit, power is also consumed.

In addition, as the performance of elements constituting circuits such as GaAs-ICs continues to improve, the timing of high-speed processing circuits that handle high-frequency signals of 5 to 10 GHz, for example, has become delicate. If the required timing to be controlled deviates, the proportion of the deviation will be large compared to the conventional circuit.

SUMMARY OF THE INVENTION In view of the above-mentioned problems, it is an object of the present invention to provide a logic circuit that realizes highly accurate timing control in response to the demand for high-speed operation.

Means for Solving the E0 Problem The present invention configures a delay circuit by a resistance component placed between the output of the front-stage gate and the input of the rear-stage gate and a capacitance component of the rear-stage gate, and The above-mentioned problems are solved by a logic circuit characterized by timing control.

Here, the resistance component is not limited to a fixed resistance component, but may be a variable resistance component.

F3 action In the logic circuit of the present invention, an RC transient phenomenon occurs due to the resistance component placed between the output of the front gate and the input of the rear gate, and the capacitance component of the rear gate. If a delay time larger than the delay time τp4 of Highly accurate timing control that meets operational requirements can be achieved.

G. Example Preferred embodiments of the present invention will be described with reference to the drawings.

In this embodiment, the resistance component of the transfer gate 1 disposed between the front-stage gate and the rear-stage gate is used as the resistance component.
Since the resistance component of the transfer gate 1 is made variable, a required delay time is formed and highly accurate timing control is realized.

First, as shown in FIG. 1, the logic circuit of this embodiment is a BFL circuit (Buffer circuit) that functions as an inverter circuit.
It is a circuit in which two stages of ED FET Logic are connected in series, and a transfer gate l that provides a variable resistance component and a control stage for controlling the transfer gate 1 are provided between the front and rear gates. There is.

The above-mentioned front stage gate has a BFL circuit configuration, and input terminal 1
0 is connected to the gate, and FET12 functions as an active load.FET13 is connected to the center point of the FE71112 and the gate is connected to the terminal opposite to the power supply side of the FET13 through a diode 15.15. The FET 14 is connected to the FET 14 and functions as an active load. Then, the diode 15 and FET1
The output of the previous stage gate is connected to the source or drain (hereinafter referred to as source/drain) of the input side of transfer gate 1 from the connection point of 4.
It's called a drain. ) is structured to be supplied to S/DI.

Further, the latter gate has a BFL circuit configuration, and has a source/drain S/Drain circuit on the output side of the transfer gate 1 to which a variable resistance component is to be provided as described later.
FET2 whose gate is connected to D2 and whose gate capacitance becomes a delay operation capacitance component; and FE which functions as an active load.
FI? having T17 and further connecting the midpoint of FET 2.17 and the gate? ,”F18 and gSFE-F
18 (7) Diode 19.1 on the terminal opposite to the power supply side
FE"F which connects through 9 and functions as an active negative e line
20. The output terminal 21 is taken out from the connection point between the diode 19 and the FET 20 mentioned above.

A transfer gate 1 and a control stage for controlling the transfer gate 1 are provided between the front-stage and rear-stage gates. First, the control stage "1" is arranged in parallel with the FET 13, the diode 15.15, and the F"ET 14 constituting the previous stage circuit, and has an FET between the power supply voltage and the ground.
4. Consists of diode 1-''6゜6 and FET3,
These are arranged in series. ”-Note F E
The gate of T4 is connected to the midpoint of knee 1-FET II, 12, similar to FET 1.3+7).
Further, the gate G of 1 is connected to the connection point between the diode 6゜6 and the FET 3 of 1.
A resistor 7 to which a ground voltage is applied is connected to the gate of FET 3, and a resistor 7 to which a ground voltage is applied is connected to the side not connected to the gate, and a diode of this control stage [controls the potential at the connection point between 6 and the FET 3] 1
In other words, the gate G of the transfer gate 1 is
16.2 An output terminal 5 for controlling the supplied electricity is connected.

Such a control stage changes the impedance of the transfer game L1 to the above Fl? : It is made variable by the DC voltage VCI supplied to the gate of T3 via the output terminal 5, and its impedance can be controlled to a desired value. Further, this control stage is arranged in parallel with the FET 13, the diode 15.15, and the FET 14, so that the -1-1 diode 15 and the FET
Fluctuations in the potential of the source/rain S/DI of Itoki I/Transfer 1-1 taken out from the connection point of 14;
The gate c' of the transfer gate 1 is taken out from the connection point between the diode 1 and the FET 3;
A change in the potential of , will show similar behavior. For this reason, only the voltage supplied to the gate of FET 3 is always reflected to control the impedance of transfer gate 1, and when the potential of transfer gate 1 is reversed due to the inversion of the potential of the previous stage gate]・G1 and the source/drain No relative fluctuation of S/DI occurs, and reliable timing control can be realized by the impedance of the transfer gate 1.

Note that the dimensions of each element in the control stage are as follows:
, diode 15.15 and FE'r14, or can be formed in a contracted and expanded pattern with similar proportions, thereby ensuring that the impedance of transfer 1 is can be controlled.

The transfer gate 1 is interposed between the front-stage gate and the rear-stage gate, and controls the delay time of the logic circuit by its variable resistance component.

In addition, as mentioned above, the gate G1 of the transfer gate 1.1 is controlled by the control stage formed in parallel with the - part of the previous stage gate, so especially when the output voltage of the previous stage gate fluctuates, the gate G1 of the transfer gate 1. However, due to the influence of the output voltage, 11
The temperature resistance value does not fluctuate. The delay time is determined by the resistance value of the relevant 1-lance gate and the F of the subsequent gate mentioned above.
It is determined by the cell capacity of E T 2. In addition, such l.
For example, a FET with a depletion mode of 1 is preferable. That is, enhancement mode FET
Then, when the source and gate potentials are the same type 4I'i,
This is because the transferate is in a blocked state.

In addition, the V of transfer gate 1 and 7 are 0.5
~1.0■ is considered appropriate.

Here, operation A1 of the logic circuit of this embodiment will be briefly explained with reference to FIG.

The input signal Vin is a rectangular wave with IR as shown in the figure. Assuming that the input is supplied from both input terminals 10, in the logic circuit of this embodiment, the delay time τpale2 of the gate of each stage plus the delay time τpa (
TG) is added, and the output signal ■. U, the total is 2τp
A delay time of d+τpa (TG) is obtained.

As described above, this delay time can be made long or short by the variable resistance component of the transfer gate 1, which is controlled by the DC voltage VCL supplied to the gate of the FET 3. For example, when obtaining a complementary lock with respect to the input signal Vin, the delay time 2τ2. When +τpa(TG) is insufficient, the delay time can be reduced by further increasing the DC voltage VCt supplied to the gate of FET 3, lowering the potential of transfer gate 1, and increasing its variable resistance component. By adjusting, a completely complementary signal waveform (delay time 2τ, 4+τpa (TGX)) can be obtained as shown by the broken line.

Furthermore, regarding the operation of the logic circuit of this embodiment, simulation results as shown in Table 1 have been obtained.

(Hereinafter, blank space) Table 1 (Vct: DC voltage supplied to FET3, 1° side: rising side, t, side: falling side) As shown in this Table 1, in the range of ±0.5V. By simply changing the DC voltage VCt, the voltage on the rising side is 290 to 190 (PSEC
For example, when processing a signal of 10 Gllz, one period is 100 PSEC, so that a sufficient required delay time can be obtained.

Note that in the above embodiments, the resistance component can be used, but the logic is not limited to this, and a fixed resistance component can be arranged between the front-stage gate and the rear-stage gate to obtain a predetermined delay time. It may be a circuit.

H0 Effects of the Invention The present invention provides R
Since a C transient phenomenon occurs, it is possible to obtain a delay time greater than 4, which is the inherent delay time τ of the preceding gate and the subsequent gate, and by changing the time constant of the transient phenomenon, an arbitrary delay time can be obtained. Can be done.

Additionally, when the resistance component is made variable using a transfer gate, etc., the delay time can be controlled by the signal supplied to the control stage, etc., achieving highly accurate timing control that meets the demands for high-speed operation. can do.

[Brief explanation of drawings]

Fig. 1 is a circuit rIδ diagram showing an example of the logic circuit of the present invention, Fig. 2 is a waveform diagram showing an example of its operation using the resistance component of the strange transfer gate 1, and Fig. 3 is a conventional logic circuit. FIG. 4 is a waveform diagram showing an example of the operation of the conventional logic circuit. 1...Transfer gate 2...FET (later gate) 3...FET (control stage) Gl...Gate electrode of transfer gate Applicant Sony Corporation agent Patent attorney
Koike Mima Sakae Tamura

Claims (1)

[Claims] A logic circuit characterized in that a delay circuit is configured by a resistance component placed between an output of a front-stage gate and an input of a rear-stage gate and a capacitance component of the rear-stage gate, and the timing of an input signal and an output signal is controlled.