JPS62290281A - Picture information recording and reproducing device - Google Patents

Abstract

PURPOSE:To perform the write of information on a picture main memory at a high speed without generating the omission of input data, by providing an auxiliary storage cell, and adding a control circuit for the auxiliary storage cell. CONSTITUTION:A picture signal inputted from a terminal 1, is changed to a bit of digital information 41 at an A/D converter 3, and is inputted to a picture main memory 6 through an auxiliary memory 4. At such a time, a memory control circuit 7 is operated setting a horizontal synchronizing signal from a terminal 2 as reference, and a row address strobe 71, a column address strobe signal 72, or an address signal 73, etc., is generated at the picture main memory 6, and is supplied to the picture main memory 6. Simultaneously, or after a time shift, a signal read out from the picture main memory 6 is changed to an analog signal at a D/A converter 8, and an analog picture signal is outputted from a terminal 9.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image recording/reproducing device, and more particularly to a device that processes digital image information using a memory.

[Conventional technology]

Conventionally, to record and reproduce high-speed, large-capacity information such as image signals, so-called dynamic random access memory (D-RAM) has been used to write and reproduce information in an operation called page mode. An example of a page mode of a memory in which a reading method is adopted will be explained with reference to the timing chart of FIG. In the figure, (a) is the row address latch strobe signal (
(hereinafter referred to as illusion), (b) is the strobe bubble number for latching the column address (hereinafter referred to as C1), (c) is address data, and (ii) is input data to the memory.Next, regarding the operation explain. In the attack operation, the row address data R1 is latched by the sword code, and the row address data R1 is latched.
Column address data Cn is latched by the 1 signal.

As a result, the memory address is (row 1 column') = (Rf
fi, On) is designated, and input data D1 is stored at this address. Then, when the next °(!A'vJ signal column address data Cn13 is latched, the memory address (row 1 column) = (R1C + 1) is specified, and the input data D1+, After setting the row address with one Tn signal, as shown in the example below, the -0AS signal is sequentially and continuously inputted.

Data can be written to the memory row specified by the RAS signal, and the speed of input information is limited by the speed of the CAS clock. Note that the maximum line address that can be specified in one block number 1 is about 10 μSθC, so when storing the horizontal scanning period in the memory for one line] Set the settings to 5~
[Problem to be solved by the invention] When storing image information in memory in the conventional page mode, it is necessary to reset the RAS signal several times during one horizontal scanning period. However, there was a problem in that the written data was missing [Lucky data D1-1 in FIG. 4].

The present invention was made to solve the above-mentioned problems, and it is an object of the present invention to provide a device that can eliminate data loss when resetting the RA S fg number.

[Failure to solve the problem]

The image information recording and reproducing apparatus according to the present invention inputs input data to the main memory via the auxiliary memory, and when reading data from the auxiliary memory to the main memory in page mode writing. The address counter is configured to stop counting when the row address in the page mode is set.

[Effect]

The image information recording and reproducing apparatus according to the present invention is provided with an auxiliary memory, and when transferring digital image information to the main memory in a page mode via the auxiliary memory, a read address counter of the auxiliary memory is set in the page mode line. Since counting is stopped when an address is set, data at that address is output twice from the auxiliary memory, thereby preventing data from being lost.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be explained with reference to the drawings.
The figure is a diagram of a system that digitizes image information and records and reproduces it in a memory. In the figure, (1) is an analog image mountain number input terminal, (2) is a horizontal synchronization signal input terminal for the image signal, (3) is a Vi analog/digital (A/D) converter, and (4) is the auxiliary memory. For example, 5-RAM
(5) is the address control circuit for the auxiliary memory (4), (6) is the main memory for one field or one frame of the image, and (7) is the control circuit for the image main memory (6). , (8) is a digital/analog (D/A') conversion word, and (9) Vi analog image signal output terminal. Figure 2 shows the auxiliary memory (4) in Figure 1.
) and its address control circuit (5), where 0]) C is the input signal to the auxiliary memory (4), (6) is the output signal from the auxiliary memory (4), and (51) is the input signal to the auxiliary memory (4). ) counter for generating Akane address, (52)
Vi same read counter, (53) u address changeover switch, (54) same switch changeover function number, (55) V
i Auxiliary memory (4) 〒) Write control signal,
(56) is a clock for both counters (5) and (52), and (57) is a horizontal synchronization signal (58) and an enable signal for the counter. FIG. 3 is a timing diagram of the operation.

As shown in the figure, the switch switching false signal El (54) and the write control signal (55) each have a write period and a read period within one clock, and the counter enable signal AEN (58) has a write period and a read period within one clock. The operation of stopping the read address counter (52) during this period using a signal that is at LOW level only during the address reset period will be described. In FIG. 1, the image signal input from the terminal (1) is converted into digital information 01) by A/D conversion 'a (3) and is input to the image main memory (6) via the auxiliary memory (4). At this time, the memory control circuit (7) operates based on the horizontal synchronization signal from the Vi terminal (2), and the image main memory (6) K row address strobe (7]), column address strobe signal (72), and °res signal (73)
etc. f is generated and supplied to the image main memory (6).

Simultaneously or time-shifted to image main memory (6)
The signal read out from ij becomes an analog signal at D/A conversion-a (8), and an analog picture PJ signal is output from the terminal (9). Next, we will explain the operation of the auxiliary memory based on Figures 2 and 3. In Figure 3, 0υ is A/
A signal is input to the auxiliary memory (4) by this clock Gυ at the D-transformation third clock.

At this time, the address (59) of the auxiliary memory (4) is the output of the write address counter (51) and the read address counter (52) switched by the switching signal S (54) of the switch circuit (53). . The counter (5) counts with the same clock (56) as the clock 01) for the A/D converter, and repeatedly outputs 0 to 7. The counter (52) operates similarly, but the count enable polarization AEN (58) causes the signal (58) to
The signal input to the auxiliary memory (4) by the A/D clock G1) is the control signal $7 (55) of the auxiliary memory (4).
When is at a low level, address (59) K is written to the corresponding address. Next, the control signal -WE (55
) becomes H1gh level, the contents of the address are output by the address (59). For example, when the data (goods) Dl-4 and the control signal (55) are low, the auxiliary memory (4) writes. mode and the 0 value of the write address (5] 1) is changed to the address (59) by the switching signal (54) of the switch (53).
When the control signal WT (55) becomes Hlgh, the auxiliary memory (4) enters the read mode and the 0 value of the read address (521) is input to the 0 address of the auxiliary memory (4). 53) switching signal (54
) is output as address (59) and Di-4, which is the content of data (6) at address 0 of auxiliary memory (4), is read out.

By the way, the row address RAS (7) of the image main memory (6)
1), the read address counter (52) of the auxiliary memory (4) is set using the enable signal ``! (58).
When stopped by , the read address counter (5
The output address (521) of 2) outputs the same address twice [value 3.3 in FIG. 3 (52])].

As a result, the content D1-1 of address value 3 is output twice to the output (6) of the auxiliary memory (4), and the first half data D1
-I Vi is lost during the reset period of the row address, and the subsequent data of Dl-1 in the latter half is stored at address C of the image main memory (6). In this way, image main memory (6)
Data D is placed at column address 0n-3 of row address RIIl.
□-4°C! llCD OIcD , COD
, CKDn-21-3'! l-11-2+1
1-I n+1 1 is stored, and the missing input data D1-1 can be compensated for. After the second row address reset, the read address is delayed by two addresses with respect to the write address of the auxiliary memory (4).

After that, the readout address is delayed by one address each time the row address is reset, and in this way, the rows are read several times in one horizontal opening period in order to compensate for the loss of input data to the image main memory (6). Input data will not be lost even if the address is reset.In addition, the address signal counter (
51) and (52) are borrowed once in one horizontal period (57
) to align the start addresses of the counters. In the above example, the counter of the auxiliary memory (4) is set to 8.
A forward counter is used, and the number of row address resets is set to f7 times or less, but the number of row address resets can be set arbitrarily by increasing the counter.Also, although we explained that it took one clock to reset the row address, This time is arbitrary, and the counter (52)
It can be controlled with the enable number.

〔Effect of the invention〕

As described above, according to the present invention, by providing an auxiliary memory element and adding a control circuit for this auxiliary memory element, it is possible to write information into the image main memory at high speed without causing any loss of input data. Become.

This is especially noticeable for continuous information such as image signals.

[Brief explanation of drawings]

FIG. 1 is a block diagram schematically showing an embodiment of the present invention;
FIG. 2 is a detailed block diagram of main parts related to the auxiliary memory of this embodiment, FIG. 3 is a timing diagram for explaining the operation of this embodiment, and FIG. 4 is a diagram for explaining the page mode operation of the conventional device. In the timing diagram, the output address counter (58) is If'1 counter enable signal. In addition, the same symbols in the figures indicate the same or corresponding parts.

Claims (1)

[Claims] (1) In a device that stores digital image information in the image information main memory in page mode and reads the image information from the main memory in real time or with a time shift, writing of the image information to the main memory is performed. This is done through the auxiliary memory, and the read address counter from the auxiliary memory stops counting during the setting period of the row address in the page mode, so that no write information is lost when setting the row address in the main memory. An image information recording and reproducing device characterized in that: