JPS62289971A - Memory using method for deinterleave execution - Google Patents

Abstract

PURPOSE:To simplify calculation of a recording address of data to shorten the deinterleave processing time by performing deinterleave simultaneously with data write to a memory. CONSTITUTION:In case that interleaved parallel data is written in the memory, the memory space is divided into eight packs correspondingly to delays of individual data and they are allowed to correspond to pack delays, and data is successively recorded on corresponding memory blocks. After one-pack components of data are recorded, the pack delay corresponding to each memory block is reduced by one and pack delay '0' is changed to 7. Recording of one pack in the memory and update of pack delays are repeated to always obtain deinterleaved data in the block of delay '0' after recording of one-pack components of data, thus shortening the deinterleave processing time.

Description

Detailed Description of the Invention 3. Detailed Description of the Invention (Field of Industrial Application) The present invention relates to a decoder device for reading subcodes from a compact disc and arranging them correctly as error correction codes.

(Prior Art) A subcode is configured in units of 24 symbols (a symbol is 6 bits), and this is called a pack.

The rules for dinterleaving are shown in Figure 4. As shown in the figure, since the maximum data delay is 7 packs, 8 packs of data are required for deinterleaving. However, excluding used data, 10 for dinterleave
It is sufficient to record only 8 symbols of data in the memory.

In the conventional method, in order to reduce wasted memory, only the necessary memory area is reserved for dinterleaving.

(Problems to be Solved by the Invention) In the conventional method described above, address calculation for memory allocation is complicated, interleaving processing takes a lot of time, and time for other correction processing etc. is reduced. This has the disadvantage that the decoder cannot be constructed without using a microprocessor with fast calculation time.

SUMMARY OF THE INVENTION An object of the present invention is to provide a dinterleaving method that eliminates the conventional drawbacks, improves the method of using memory for dinterleaving, and reduces the time required to generate addresses in the memory.

(Means for Solving the Problems) The memory usage method for dinterleaving of the present invention makes the memory space correspond to the delay of individual data when writing interleaved parallel data to memory. Dinterleaving is performed at the same time as data is written to the memory by means of writing data in such a manner and by means of updating the correspondence relationship for each predetermined block.

(Function) The present invention has the following advantages due to the above-described memory division, correspondence between memory and pack delay, and update of pack delay. That is, by recording one pack in the memory and repeatedly updating the pack delay, data dinterleaved into zero delay blocks is always obtained after recording one pack of data.

(Example) An example of the present invention will be described based on FIGS. 1 to 3.

FIG. 1 shows the correspondence between memory blocks and pack delays and their updating in the present invention.

First, the memory is divided into 8 packs and a pack delay is assigned to each pack. Data is sequentially recorded in corresponding memory blocks. After one pack of data has been recorded,
The pack delay corresponding to each memory is decreased by one. However, pack delay 2 is changed to 7.

FIG. 2 shows the signal from the CD player.

FIGS. 3(a) and 3(b) are flowcharts of one embodiment of the present invention. FIG. 3(a) shows the data import routine;
FIG. 3(b) shows the S, S1 synchronization detection routine.

In FIG. 3(a), 11 is address calculation, and the address is obtained from the order of symbols in one pack and the start address of the block corresponding to its delay, and 12 is used to record data. When the symbols in the pack are counted at step 13 and all the data of one pack has been recorded, the symbol counter is initialized at step 14, and the memory block and pack delay are updated at step 15. If recording of one pack of data is not completed, 1 is added to the symbol counter at 16=3-.

In FIG. 3(b), 21 resets the symbol counter, 22 indicates S, and every time S1 is counted twice, the correspondence between memory blocks and pack delays is initialized at 23, S, 24, etc. Reset the S1 synchronization counter. Also, S at 25. , increments the S1 counter.

(Effects of the Invention) According to the present invention, it is easy to calculate the data recording address, the dinterleave processing time can be shortened, and the practical effects are great.

[Brief explanation of drawings]

Figure 1 is a diagram showing the correspondence between memory blocks and pack delays and their updating in the present invention, Figure 2 is a signal from a CD player, and Figures 3 (a) and (b) are flowcharts of an embodiment of the present invention. , FIG. 4 is a diagram showing the conventional dinterleave rule. Fig. 1 Fig. 2;
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Claims (1)

[Claims] When interleaved parallel data is written to memory, the memory space is divided to correspond to the delay of each data and the data is written, and the above-mentioned correspondence relationship is updated for each predetermined data block. , a memory usage method for deinterleaving, characterized by performing deinterleaving at the same time as data is written to memory.