JPS6228789A - Graphic display - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to graphic displays, and more particularly to a frame buffer configuration control scheme for graphic displays.

[Conventional technology]

Conventional graphic displays are constructed by arranging a large number of frame buffers with a storage capacity corresponding to the maximum display screen area in order to enable simultaneous multi-color representation of graphics. For example, the maximum display screen area is 1280 x 102
To perform simultaneous expression of 4 dots and 1024 colors, 128
Ten frame buffers of 0 x 1024 dots are prepared.

[Problem that the invention seeks to solve]

The display screen of a graphic display is generally divided into a graphic display area and a menu display area, as shown in FIG. For example, the maximum display screen area is 1280
In the case of X 1024 dots, the figure display area is 1024
X 1024 dots, menu display area is 256 X
Divided into 1024 dots. Although simultaneous multicolor display is required in the graphic display area, in overwhelming cases a single color is sufficient for menu display. For this reason, a conventional graphic display in which a frame buffer having a storage capacity necessary for displaying a full screen display area including a graphic display area and a menu display area is used as a separate window capable of simultaneously expressing multiple colors is wasteful. For example, when 1024 colors are simultaneously expressed using the screen configuration shown in FIG. 2, 1024 x 256 x (10-1) bits are wasted.

The object of the invention is to provide a graphic display which improves the above-mentioned drawbacks.

[Means for solving problems]

The present invention provides a graphic display in which a screen display area is divided into a graphic display area and a menu display area, including a graphic display frame buffer that stores display patterns for the graphic display area and a menu display frame buffer that stores display patterns for the menu display area. and means for generating a video signal by switching between the two types of frame buffers according to the display screen address.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention,
A display control unit 1 that performs display processing for the entire graphic display, a buffer address counter 2 that specifies the display screen position, and a decoder 3 that generates a graphic display selection signal 24 and a menu display selection signal 25 from the address indicated by the contents of the buffer address counter 2. , a timing circuit 4 that generates a count pulse 30 for the buffer address counter 2 and a synchronization signal 26 for the display section, n graphic display frame buffers 5-1 to 5-n, a menu display frame buffer 6, and an AND gate 7-1 to ? -n and 8, read information 22 from frame buffers 5-1 to 5-n and 6
-1 to 22-n and 23 to a video signal 27, and a display section 10.

The frame buffers are divided into two types: n graphic display frame buffers 5-1 to 5-n and one menu display frame buffer 6. The menu display frame buffer stores the display pattern for the menu display area. In the case of simultaneous representation of 1024 colors, n=10. For example 1280
The maximum display screen area of 1024 dots is 1024
Graphic display area of 1024 x 1 dot and 256 x 1
024 dot menu display area, each graphic display frame buffer 5-1 to 5-10 has a storage capacity of 1024 x 10 required for displaying the graphic display area.
24 bits 1, menu display frame buffer 6
is the storage capacity required to display the menu display area 256
It has 1024 bits.

The output terminals of the graphic display frame buffers 5-1 to 5-n are connected to one input terminal of the AND gates 7-1 to 7-n, respectively, and the output terminal of the menu display frame buffer 6 is connected to one of the input terminals of the AND gates 8. is connected to the input terminal of The other input terminals of the AND gates 7-1 to 7-n are connected to the output terminal of the decoder 3 that outputs a graphic display selection signal, and the other input terminal of the AND gate 8 is connected to the output terminal of the decoder 3.
is connected to the output terminal that outputs the menu display selection signal.

' Next, the operation of the graphic display of this embodiment will be explained. When rewriting the display screen, display control unit 1
is written information 20. Buffer specification information 21° Specifies address information 28. The write information 20 is information for writing a display pattern from the display control unit 1 to the frame buffers 5-1 to 5-n and U6. Frame buffer specification information 2
1 is information for specifying a frame buffer in write mode. Further, address information 28 is information for specifying a write address on the display screen. Based on this information,
A desired display pattern is written into frame buffers 5-1 to 5-n and 6.

In the display mode, the display control unit 1 outputs a mode designation signal 29 to the timing circuit 4 to designate the read mode of the frame buffer. When the mode designation signal 29 is input to the timing circuit 4, the timing circuit generates a count pulse 30 for the buffer address counter 2 and a synchronization signal 26 for the display section 10. The buffer address counter 2 automatically updates its contents using the count pulse 30. At this time, a graphic display selection signal 24 and a menu display selection signal 25 are switched and outputted by the decoder 3 according to the display screen position specified by the buffer address counter 2. The graphic display selection signal 24 is the AND gate 7-1~? -n input terminal, and the menu display selection signal 25 is input to the AND gate 8 input terminal.

When the graphic display selection signal 24 is output, the AND gates 7-1 to 7-n are connected to the graphic display frame buffer 5.
The successive information from -1 to 5-n is sent to the video signal converter 9, converted into a video signal 27, and inputted to the 7 display section 10.

On the other hand, when the menu display selection signal 25 is being output, the AND gate 8 sends the successive information from the menu display frame buffer 6 to the video signal converting section 9, converting it into a video signal 27, and inputting it to the display section 10. Graphics and menus are displayed on the display section 10 based on these video signals and the synchronization signal input from the timing circuit 4.

〔Effect of the invention〕

As explained above, the present invention has the effect that by dividing the screen display area into a figure display area and a menu display area and providing a frame buffer corresponding to each area, a graphic display can be configured with less waste of memory elements as a whole. There is.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is an example of division of a display screen. 1...Display control unit 2...Buffer address counter 3...
... Decoder 4 ... Timing circuits 5-1 to 5-n... Graphic display frame buffer 6 ・
...Menu display frame buffer 7-1 to 7
-n, 8 ・・・ And gate 9 ・・・・・・
Video signal converter 10...Display section

Claims (1)

[Claims] (1) In a graphic display in which the screen display area is divided into a figure display area and a menu display area, there is a figure display frame buffer that stores the display pattern for the figure display area, and a menu display frame buffer that stores the display pattern for the menu display area. and means for generating a video signal by switching between the two types of frame buffers according to a display screen address.