JPS62280056A - Led array head - Google Patents
Led array headInfo
- Publication number
- JPS62280056A JPS62280056A JP61123334A JP12333486A JPS62280056A JP S62280056 A JPS62280056 A JP S62280056A JP 61123334 A JP61123334 A JP 61123334A JP 12333486 A JP12333486 A JP 12333486A JP S62280056 A JPS62280056 A JP S62280056A
- Authority
- JP
- Japan
- Prior art keywords
- wiring pattern
- chip
- driving
- substrate
- led array
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 239000010408 film Substances 0.000 claims 1
- 239000010409 thin film Substances 0.000 claims 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 abstract description 4
- 239000000919 ceramic Substances 0.000 abstract description 4
- 229910052709 silver Inorganic materials 0.000 abstract description 4
- 239000004332 silver Substances 0.000 abstract description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 3
- 238000005476 soldering Methods 0.000 abstract description 2
- 238000006664 bond formation reaction Methods 0.000 abstract 1
- 230000002349 favourable effect Effects 0.000 abstract 1
- 229910000679 solder Inorganic materials 0.000 description 6
- 238000004806 packaging method and process Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000009736 wetting Methods 0.000 description 1
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
- B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
- B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
- B41J2/435—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of radiation to a printing material or impression-transfer material
- B41J2/447—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of radiation to a printing material or impression-transfer material using arrays of radiation sources
- B41J2/45—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of radiation to a printing material or impression-transfer material using arrays of radiation sources using light-emitting diode [LED] or laser arrays
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、発光ダイオードアレイチップとその駆動用Ｉ
Ｃチップを搭載したＬＥＤアレイヘッドの改良に関する
。[Detailed Description of the Invention] [Industrial Application Field] The present invention provides a light emitting diode array chip and an I/O device for driving the same.
This invention relates to improvement of an LED array head equipped with a C chip.
〔従来の技術Ｊ
例えばファクシｉす等の記録方式として発光ダイオード
アレイチップ（以下ＬＥＤ７レイチツプという）を搭載
したＬＢＤアレイヘッドが使用される。[Prior Art J] For example, an LBD array head equipped with a light emitting diode array chip (hereinafter referred to as LED7 array chip) is used as a recording method for facsimile machines and the like.
このＬＥＤアレイヘッドは、基板上に配線パターンを形
成し、ＬＦｉＤアレイチップとその発光素子を駆動させ
るための駆動用ＩＣチップを多数個搭載し、それぞれワ
イヤボンディング形式で接続実装されている。In this LED array head, a wiring pattern is formed on a substrate, and a large number of driving IC chips for driving an LFiD array chip and its light emitting elements are mounted, and the chips are connected and mounted using wire bonding.
従来の発光ダイオードを用いたプリンターは、特開昭６
０−１１６４７９号忙記載のよりに、基板上に発光ダイ
オードアレイチップとその駆動用ＩＣチップを搭載しそ
の接続はワイヤボンディング形式にて構成していた。A printer using conventional light emitting diodes was developed in Japanese Patent Application Laid-open No. 6
As described in No. 0-116479, a light emitting diode array chip and an IC chip for driving the light emitting diode array chip were mounted on a substrate, and their connections were configured by wire bonding.
上記従来技術は、多数個の発光ダイオードアレイチップ
とその駆動用ＩＣチップを配線パターンの形成された基
板上に搭載実装するために、まず銀ペーストを介してダ
イボンディングを行員、ワイヤボンディングを行なって
いた。その結果例えばＢ４サイズで記録密就が４００ド
ツト／インチのＬＥＤアレイヘッドを何処すると、その
すべての接続をワイヤボンディング形式で行う構成にし
た場合は、１ヘッド当シ約９７００本のワイヤ接続とな
）、チップ周囲釦はポンディングパッドを配置する必要
がある。そのため高密度実装化を考慮した場合は、配線
パターンレイアウト的にも不利となル、ワイヤボンディ
ングの作業効率とその接続信頼性及び基板配線パターン
形成のプロセス効率の点で問題があった。本発明の目的
は上記した問題点を解決することにある。In the above conventional technology, in order to mount and mount a large number of light emitting diode array chips and their driving IC chips on a substrate on which a wiring pattern is formed, die bonding is first performed using silver paste, and then wire bonding is performed. Ta. As a result, for example, if a B4 size LED array head with a recording density of 400 dots/inch is configured to make all connections using wire bonding, there will be approximately 9,700 wire connections per head. ), it is necessary to place a bonding pad on the button around the chip. Therefore, when high-density packaging is taken into consideration, it is disadvantageous in terms of wiring pattern layout, and there are problems in terms of wire bonding work efficiency, connection reliability, and process efficiency of substrate wiring pattern formation. An object of the present invention is to solve the above-mentioned problems.
〔問題を解決するための手段Ｊ
上記の目的は、搭載される駆動用ＩＣチップをフェイス
ダウン状にし、フリップチップボンディングによシ基板
上に形成した配線パターンのパッドに接続するように構
成することによって達成される。[Means to Solve the Problem J The above purpose is to configure the drive IC chip to be mounted face down and to connect it to the pad of the wiring pattern formed on the substrate by flip chip bonding. achieved by.
又、配線パターンの全部又は一部を駆動用ＩＣチップを
搭載するエリア下部にも配置することを特徴とするもの
である。Further, the present invention is characterized in that all or part of the wiring pattern is also arranged below the area where the driving IC chip is mounted.
以上のように構成することにより駆動用ＩＣチップの接
続端子は、はんだバングにて形成し、基板配線パターン
のパッド部は駆動用ＩＣチップの接続端子配置寸法に合
わせ、かつはんだヌレ性の良い金属膜で形成しておき、
駆動用ＩＣチップをフェイスダウン状に、基板配線パタ
ーンのパッド部に搭載し、はんだリフロー法によって同
時に多数個の駆動用ＩＣチップがはんだ接続される。Ｌ
ＥＤアレイチップのみワイヤボンディング形式で接続す
れば、ワイヤ接続本数は半減し、作業効率と接続信頼性
が向上する。さらに駆動用ＩＣチップに合わせた基板配
線のパッド部を設け、その配線パターンの一部あるいは
すべてが、駆動用ＩＣチップを搭載するエリア下部にも
配置させることにより、高密度化実装化を考慮した配線
パターンレイアウトが可能となシ、基板の配線パターン
形成プロセスの効率が向上する。With the above configuration, the connection terminals of the drive IC chip are formed with solder bangs, and the pad portion of the board wiring pattern is made of a metal that matches the arrangement dimensions of the connection terminals of the drive IC chip and has good solder wetting properties. Formed with a membrane,
The driving IC chips are mounted face down on the pad portions of the board wiring pattern, and a large number of driving IC chips are simultaneously soldered and connected by a solder reflow method. L
If only the ED array chips are connected using wire bonding, the number of wires to be connected can be halved, improving work efficiency and connection reliability. Furthermore, by providing a pad part for the board wiring that matches the drive IC chip, and placing part or all of the wiring pattern below the area where the drive IC chip is mounted, high-density packaging is considered. Wiring pattern layout is possible, and the efficiency of the wiring pattern forming process on the board is improved.
〔実施例」
以下、本発明の一実施例を第１図及び第２図を用いて説
明する。第１図は本ＬＥＤアレイヘッドの一部分の平面
図、第２図はその断面図を示す。[Example] An example of the present invention will be described below with reference to FIGS. 1 and 2. FIG. 1 is a plan view of a portion of the present LED array head, and FIG. 2 is a sectional view thereof.
セラミック基板１上の中央部の共通電極部２に銀ベース
ト３を介してＬＥＤアレイチップ４が搭載され、金ワイ
ヤ５にて配線パターン６に接続されて込る。一方配線パ
ターン６と対向して、制限抵抗７を経由して、駆動用Ｉ
Ｃチップ８がはんだバンプ９にて接続して因る。さらに
駆動用ＩＣチップ８け外部との接続端子１０へ引出され
ている。An LED array chip 4 is mounted on a common electrode section 2 at the center of a ceramic substrate 1 via a silver base 3, and connected to a wiring pattern 6 with gold wires 5. On the other hand, the drive I
The C chip 8 is connected with a solder bump 9. Furthermore, eight driving IC chips are drawn out to external connection terminals 10.
配線パターン６は、セラミック基板１上にＣｒ−８ｌｊ
刊制限抵抗７の膜を介して、Ｃｒ Ｏｊ Ａｍ 、 Ｃ
ｕ ４μｍ 。The wiring pattern 6 is made of Cr-8lj on the ceramic substrate 1.
Through the film of limiting resistor 7, Cr Oj Am, C
u 4μm.
ＡｕＯ，３μｍの計４層構成で、それぞれスパッタリン
グ法にて膜形成を行い、更にフォトエツチング法にてパ
ターン形成を行う。そして、駆動用ＩＣチップ８を７リ
ツズボンデイングするパッドとＬＰＩＤアレイチップ４
をワイヤボンディングするパッドを共通の膜で形成して
いる。It has a total of four layers of AuO with a thickness of 3 μm, and each film is formed by sputtering, and a pattern is formed by photoetching. Then, the pad for bonding the driving IC chip 8 and the LPID array chip 4.
The pads for wire bonding are formed using a common film.
これＫより％２種類のボンディング工法が可能なポンデ
ィングパッドを共通膜にて構成し、膜形成及びパターン
プロセスの簡略化と効率化が図られる。From this K, bonding pads that can be used with %2 types of bonding methods are constructed from a common film, thereby simplifying and increasing the efficiency of film formation and patterning processes.
さらに駆動用ＩＣチップ８はフェイスダウン状にフリッ
プチッズボンデインク形成で搭載し、はんだす７０−法
にて多数個同時に接続することが可能となシ、作業効率
が向上し、ワイヤボンディング形式と比較して接続信頼
性も向上する。さらに配線パターン６の一部は、駆動用
ＩＣチップ８の搭載エリア下部にも配置できるため、配
線パターン乙のレイアウト面で有利とな〕、基板配線パ
ターン形成プロセスの効率が向上する。Furthermore, the driving IC chips 8 are mounted face-down using flip chip bonding, making it possible to connect a large number of them at the same time using the 70-soldering method, which improves work efficiency and enables wire bonding. In comparison, connection reliability is also improved. Further, a part of the wiring pattern 6 can be placed under the mounting area of the driving IC chip 8, which is advantageous in terms of the layout of the wiring pattern B], and improves the efficiency of the substrate wiring pattern forming process.
〔発明の効果Ｊ
本発明によれば、駆動用ＩＣチップはフェイスダウン状
にフリップチッズボンディング形式で、はんだリフロー
法にて多数個同時ＶＣ接続することができるため、ワイ
ヤボンディング形式と比較して作業効率が大巾に向上す
る。さらに接続信頼性における比較でも勝ってお）、か
つ高密度実装化を考慮した場合の配線パターンレイアウ
トの面でも有利となる等の効果がある。[Effects of the Invention J According to the present invention, a large number of drive IC chips can be simultaneously connected to VC using the solder reflow method using the flip chip bonding method in a face-down manner, compared to the wire bonding method. Work efficiency is greatly improved. Furthermore, it is superior in terms of connection reliability) and is advantageous in terms of wiring pattern layout when high-density packaging is considered.
第１図は本発明の一実施例であるＬＥＤアレイへ、ドの
平面図、第２図はその縦断面図である。
なおこれらの図の縦横厚さ等の縮尺倍率は任意である。
１・・・セラミック基板、２・・・共通電極部、３・・
・銀ベースト、４・・・ＬＥＤアレイチップ、５・・・
金ワイヤ、６・・・配線パターン、７・・・制限抵抗、
８・・・駆動用ＩＣチップ、９・・・はんたバンプ、１
０・・・外部接続端子。FIG. 1 is a plan view of an LED array according to an embodiment of the present invention, and FIG. 2 is a longitudinal sectional view thereof. Note that the scale factors such as the vertical and horizontal thickness of these figures are arbitrary. 1...Ceramic substrate, 2...Common electrode part, 3...
・Silver base, 4... LED array chip, 5...
Gold wire, 6... Wiring pattern, 7... Limiting resistance,
8...Drive IC chip, 9...Solder bump, 1
0...External connection terminal.
Claims (1)
を形成し、その上に発光ダイオード素子アレイチップ及
び駆動用ＩＣチップを搭載したＬＥＤアレイヘッドにお
いて、前記駆動用ＩＣチップをフェイスダウン状にし、
フリップチップボンディングにより前記基板上に形成し
た配線パターンのパッドに接続したＬＢＤアレイヘッド
。 ２、特許請求の範囲第１項記載の配線パターンにおいて
、該配線パターンの全部又は一部を駆動用ＩＣチップを
搭載するエリア下部にも配置することを特徴とするＬＥ
Ｄアレイヘッド。[Claims] 1. In an LED array head in which a wiring pattern is formed on a substrate by a thin film or thick film process, and a light emitting diode element array chip and a driving IC chip are mounted thereon, the driving IC chip face down,
An LBD array head connected to pads of a wiring pattern formed on the substrate by flip chip bonding. 2. An LE characterized in that, in the wiring pattern according to claim 1, all or part of the wiring pattern is also arranged below the area where the driving IC chip is mounted.
D array head.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61123334A JPS62280056A (en) | 1986-05-30 | 1986-05-30 | Led array head |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61123334A JPS62280056A (en) | 1986-05-30 | 1986-05-30 | Led array head |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62280056A true JPS62280056A (en) | 1987-12-04 |
Family
ID=14857987
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61123334A Pending JPS62280056A (en) | 1986-05-30 | 1986-05-30 | Led array head |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62280056A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6603258B1 (en) * | 2000-04-24 | 2003-08-05 | Lumileds Lighting, U.S. Llc | Light emitting diode device that emits white light |
-
1986
- 1986-05-30 JP JP61123334A patent/JPS62280056A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6603258B1 (en) * | 2000-04-24 | 2003-08-05 | Lumileds Lighting, U.S. Llc | Light emitting diode device that emits white light |
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