JPS62272561A - 1-transistor type memory cell - Google Patents

1-transistor type memory cell

Info

Publication number
JPS62272561A
JPS62272561A JP61115621A JP11562186A JPS62272561A JP S62272561 A JPS62272561 A JP S62272561A JP 61115621 A JP61115621 A JP 61115621A JP 11562186 A JP11562186 A JP 11562186A JP S62272561 A JPS62272561 A JP S62272561A
Authority
JP
Japan
Prior art keywords
type
gt
lt
polysilicon
formed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61115621A
Inventor
Keitaro Fujimori
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP61115621A priority Critical patent/JPS62272561A/en
Publication of JPS62272561A publication Critical patent/JPS62272561A/en
Application status is Pending legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/108Dynamic random access memory structures
    • H01L27/10805Dynamic random access memory structures with one-transistor one-capacitor memory cells
    • H01L27/10838Dynamic random access memory structures with one-transistor one-capacitor memory cells the capacitor and the transistor being in one trench
    • H01L27/10841Dynamic random access memory structures with one-transistor one-capacitor memory cells the capacitor and the transistor being in one trench the transistor being vertical

Abstract

PURPOSE:To obtain a memory cell for performing a DRAM of approx. 64Mbit by using a trench type capacitor buried through a thin insulating film in a P<+> type substrate, and an N-channel MIS transistor of vertical SOI structure having an upper part as a source electrode. CONSTITUTION:A trench type capacitor of N<+> type polysilicon 24 buried through a thin insulating film 25 in a P<+> type substrate 21, and an N-channel MIS transistor of vertical SOI structure having the upper part of the polysilicon 24 as a source electrode are employed. For example, a trench structure is formed by RIE on the substrate 21, and the polysilicon 34, a P<-> type polysilicon 23 and an N<+> type polysilicon 22 are formed through the film 25. Further, after a field oxide film 28 and a gate oxide film 26 are formed, a gate electrode 27, a word line 29 and an interlayer insulating film 30 are formed, a contact hole is then opened to form a bit line 31, thereby obtaining a 1-transistor type memory cell in which a vertical MOS transistor is laminated on the trench type data storage capacitor.
JP61115621A 1986-05-20 1986-05-20 1-transistor type memory cell Pending JPS62272561A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61115621A JPS62272561A (en) 1986-05-20 1986-05-20 1-transistor type memory cell

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61115621A JPS62272561A (en) 1986-05-20 1986-05-20 1-transistor type memory cell

Publications (1)

Publication Number Publication Date
JPS62272561A true JPS62272561A (en) 1987-11-26

Family

ID=14667186

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61115621A Pending JPS62272561A (en) 1986-05-20 1986-05-20 1-transistor type memory cell

Country Status (1)

Country Link
JP (1) JPS62272561A (en)

Cited By (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5181089A (en) * 1989-08-15 1993-01-19 Matsushita Electric Industrial Co., Ltd. Semiconductor memory device and a method for producing the same
US5550396A (en) * 1992-01-24 1996-08-27 Mitsubishi Denki Kabushiki Kaisha Vertical field effect transistor with a trench structure
US8861247B2 (en) 2009-04-27 2014-10-14 Micron Technology, Inc. Techniques for providing a direct injection semiconductor memory device
US8873283B2 (en) 2005-09-07 2014-10-28 Micron Technology, Inc. Memory cell and memory cell array having an electrically floating body transistor, and methods of operating same
US8947965B2 (en) 2009-07-27 2015-02-03 Micron Technology Inc. Techniques for providing a direct injection semiconductor memory device
US8964479B2 (en) 2010-03-04 2015-02-24 Micron Technology, Inc. Techniques for sensing a semiconductor memory device
US8982633B2 (en) 2009-05-22 2015-03-17 Micron Technology, Inc. Techniques for providing a direct injection semiconductor memory device
US9019759B2 (en) 2010-03-15 2015-04-28 Micron Technology, Inc. Techniques for providing a semiconductor memory device
US9019788B2 (en) 2008-01-24 2015-04-28 Micron Technology, Inc. Techniques for accessing memory cells
US9064730B2 (en) 2009-03-04 2015-06-23 Micron Technology, Inc. Techniques for forming a contact to a buried diffusion layer in a semiconductor memory device
US9093311B2 (en) 2009-03-31 2015-07-28 Micron Technology, Inc. Techniques for providing a semiconductor memory device
US9142264B2 (en) 2010-05-06 2015-09-22 Micron Technology, Inc. Techniques for refreshing a semiconductor memory device
US9240496B2 (en) 2009-04-30 2016-01-19 Micron Technology, Inc. Semiconductor device with floating gate and electrically floating body
US9257155B2 (en) 2007-05-30 2016-02-09 Micron Technology, Inc. Integrated circuit having voltage generation circuitry for memory cell array, and method of operating and/or controlling same
US9263133B2 (en) 2011-05-17 2016-02-16 Micron Technology, Inc. Techniques for providing a semiconductor memory device
US9276000B2 (en) 2007-03-29 2016-03-01 Micron Technology, Inc. Manufacturing process for zero-capacitor random access memory circuits
US9331083B2 (en) 2009-07-10 2016-05-03 Micron Technology, Inc. Techniques for providing a semiconductor memory device
US9553186B2 (en) 2008-09-25 2017-01-24 Micron Technology, Inc. Recessed gate silicon-on-insulator floating body device with self-aligned lateral isolation
US9559216B2 (en) 2011-06-06 2017-01-31 Micron Technology, Inc. Semiconductor memory device and method for biasing same
US9812179B2 (en) 2009-11-24 2017-11-07 Ovonyx Memory Technology, Llc Techniques for reducing disturbance in a semiconductor memory device

Cited By (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5181089A (en) * 1989-08-15 1993-01-19 Matsushita Electric Industrial Co., Ltd. Semiconductor memory device and a method for producing the same
US5550396A (en) * 1992-01-24 1996-08-27 Mitsubishi Denki Kabushiki Kaisha Vertical field effect transistor with a trench structure
US8873283B2 (en) 2005-09-07 2014-10-28 Micron Technology, Inc. Memory cell and memory cell array having an electrically floating body transistor, and methods of operating same
US9276000B2 (en) 2007-03-29 2016-03-01 Micron Technology, Inc. Manufacturing process for zero-capacitor random access memory circuits
US9257155B2 (en) 2007-05-30 2016-02-09 Micron Technology, Inc. Integrated circuit having voltage generation circuitry for memory cell array, and method of operating and/or controlling same
US9019788B2 (en) 2008-01-24 2015-04-28 Micron Technology, Inc. Techniques for accessing memory cells
US9553186B2 (en) 2008-09-25 2017-01-24 Micron Technology, Inc. Recessed gate silicon-on-insulator floating body device with self-aligned lateral isolation
US9064730B2 (en) 2009-03-04 2015-06-23 Micron Technology, Inc. Techniques for forming a contact to a buried diffusion layer in a semiconductor memory device
US9093311B2 (en) 2009-03-31 2015-07-28 Micron Technology, Inc. Techniques for providing a semiconductor memory device
US8861247B2 (en) 2009-04-27 2014-10-14 Micron Technology, Inc. Techniques for providing a direct injection semiconductor memory device
US9425190B2 (en) 2009-04-27 2016-08-23 Micron Technology, Inc. Techniques for providing a direct injection semiconductor memory device
US9240496B2 (en) 2009-04-30 2016-01-19 Micron Technology, Inc. Semiconductor device with floating gate and electrically floating body
US8982633B2 (en) 2009-05-22 2015-03-17 Micron Technology, Inc. Techniques for providing a direct injection semiconductor memory device
US9331083B2 (en) 2009-07-10 2016-05-03 Micron Technology, Inc. Techniques for providing a semiconductor memory device
US9076543B2 (en) 2009-07-27 2015-07-07 Micron Technology, Inc. Techniques for providing a direct injection semiconductor memory device
US8964461B2 (en) 2009-07-27 2015-02-24 Micron Technology, Inc. Techniques for providing a direct injection semiconductor memory device
US9679612B2 (en) 2009-07-27 2017-06-13 Micron Technology, Inc. Techniques for providing a direct injection semiconductor memory device
US8947965B2 (en) 2009-07-27 2015-02-03 Micron Technology Inc. Techniques for providing a direct injection semiconductor memory device
US9812179B2 (en) 2009-11-24 2017-11-07 Ovonyx Memory Technology, Llc Techniques for reducing disturbance in a semiconductor memory device
US8964479B2 (en) 2010-03-04 2015-02-24 Micron Technology, Inc. Techniques for sensing a semiconductor memory device
US9524971B2 (en) 2010-03-15 2016-12-20 Micron Technology, Inc. Techniques for providing a semiconductor memory device
US9019759B2 (en) 2010-03-15 2015-04-28 Micron Technology, Inc. Techniques for providing a semiconductor memory device
US9142264B2 (en) 2010-05-06 2015-09-22 Micron Technology, Inc. Techniques for refreshing a semiconductor memory device
US9263133B2 (en) 2011-05-17 2016-02-16 Micron Technology, Inc. Techniques for providing a semiconductor memory device
US9559216B2 (en) 2011-06-06 2017-01-31 Micron Technology, Inc. Semiconductor memory device and method for biasing same

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