JPS6226842A - Formation of multilayer interconnection - Google Patents

Abstract

PURPOSE:To stack numerous layers, and also to prevent the wiring resistance from augmenting due to the narrowing of the wirings by a method wherein a metal film is patterned, an insulating film is formed on the whole surface, the surface thereof is flattened and an etching is performed until the surfaces of the metal film patterns are exposed. CONSTITUTION:An Al film 27 is deposited on the whole surface of an Si substrate 21, whereon the forming process of the element parts is already finished, then a dry etching is performed on the Al film 27 using the resist pattern of the Al film 27 as a mask and Al film patterns 28 are formed on each impurity diffusion region 25 as the connecting layers between each impurity diffusion region 25 and the first-layer wiring layer. An Si nitride film 29 is deposited on the whole surface, and moreover, an organic resist 30 is applied to flatten the surface. After that, the resist 30 and the Si nitride film 29 are etched back until the surfaces of the Al film patterns 28 are made to expose. The Si nitride film 29 is left in the same height as the surfaces of the Al film patterns 28. As the result, the flat surface is obtained. After that, a series of these processes are repeated.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for forming multilayer wiring in a semiconductor device.

(Prior Art) Conventionally, in a semiconductor device, multilayer wiring is formed in the following manner. First, a metal such as M is deposited on the entire surface of the substrate by a suction method or the like, and then this metal is notared by a lithography method. Next, absolute RR is deposited on this by CVD method or the like. Then, an interlayer connection hole (byer hole) is formed in the insulating film by phosphorography, metal is deposited again, and 79 turns are performed by phosphorography. After repeating one or more steps several times, a protective film is deposited to complete the multilayer wiring manufacturing process.

FIG. 3 is a cross-sectional view showing an example of a multilayer wiring structure manufactured by such a conventional method. In this diagram,
1 is a silicon substrate, 2 is a thick oxide film for element isolation, 3 is a dirt electrode, 4 is an R-TM film, 5 is an impurity diffusion region as a drain and drain, 6 is a PSG film as a passivation film, 7 1 is a first layer of metal wiring, 8 is a SiN film as an insulating film between the eyebrows, 9 is a second layer of metal wiring, and 10 is a protective film.

(Problem to be solved by the invention) However, as is clear from Figure 3, in the conventional method as described above, there is inevitably a difference in level where there is wiring and where there is no wiring, so it is necessary to use many layers. It was difficult to accumulate.

Further, there was a drawback that the wiring became thinner at the step at the connection part (the step coverage of the 7J position film by the Sonon-tsuta method was poor at the step) and the wiring resistance increased.

This invention was made in view of the above points, and its purpose is to form a multilayer wiring that can stack three or four or more layers and prevent an increase in wiring resistance due to wiring measurement. The purpose is to provide a method.

(Means for Solving the Problems) This invention includes a step of forming a gold JtA film on the entire surface, a step of patterning the metal film, forming an insulating film on the entire surface including the metal film/gut pattern, and A series of steps consisting of a step of flattening the surface and a step of etching the insulating film until the surface of the metal film pattern is exposed is repeated for each wiring layer or connection layer to form a multilayer wiring.

(Function) In this way, a flat surface is always ensured by the insulating film remaining after etching, and since the connection layer is formed separately from the wiring layer, there is no difference in level at the connection portion.

(Example) An embodiment of the present invention will be described below with reference to FIG.

FIG. 1(a) shows the state where the forming process of the element part is completed, 21 is a silicon substrate, 22 is a thick oxide film for element isolation, 23 is an r-to electrode, 24 is an r-to oxide film, 25 is an impurity diffusion region serving as a source/drain, and 26 is a PSG film serving as a compression film.

After that, AI! is applied to the entire surface of the silicon substrate 21 as shown in FIG. 1(b). The film 27 (metal film) is placed in a vertical position using the vine method.

Next, AI! Although not shown above, a resist is applied on the film 2 and the film 7 is turned by photolithography, and then the A/film 27 is dry-etched using the resist non-turn as a mask. As shown in c), an AI! membrane notarne 28 is formed.

Here, AI! I! The turn 28 is connected to each impurity diffusion region 2.
5 as a connection layer between this and a first layer wiring layer to be described later.

Next, after removing the resist pattern, a silicon nitride film 29 (insulating film) is deposited on the entire surface including the M film/zetan pattern 28 by plasma CVD as shown in FIG. 1(d). An organic resist 30 is applied onto the silicon nitride film 29 to flatten the surface.

After that, resist 30 and silicon nitride JljJ29,
As shown in FIG. 1(e), etch packing is performed until the surface of the A/membrane knock turn 28 is exposed. This etch pack is performed at CF4102 at 0.1 to 0.5 Torr, and the resist 30 and silicon nitride film 29 are etched at a constant speed. With this etch pack, the silicon nitride film 29 is
I! I! The periphery of the turn 28 is left flush with the surface of the A// pattern 28, resulting in a flat surface.

After that, repeat the above series of steps. In other words, A!
A film 31 is deposited (FIG. 1(f)), a non-turning film 32 is deposited (FIG. 1(g)), and then a silicon nitride film 32 is deposited, and a resist 33 is applied thereon. )) After that, the resist 33 and silicon nitride film 32 are etch-packed (FIG. 1(i)). By repeating this series of steps), here, the above A
! ! An A// pattern 34 as a first layer wiring layer connected to the film A turn 28 is formed, and a flat surface shape is obtained by using the silicon nitride film 32 remaining after etching.

After that, AI! I! In order to lower the resistance of the connection between the turn 28 and the fourth turn 34 of the M film, heat treatment is performed at 450° C. for 20 minutes in N snow.

Thereafter, in this embodiment, the above series of steps is repeated twice, with the above heat treatment step added at the end of each step. Tsumashi, 1st repetition 9 times Figure 1 (j), (g)
) to form an M conversion layer 35 as an interlayer connection layer, and etching the surface to remove the remaining silicon nitride film 36.
Figure 1(1)
, (e)), an AJ film pattern 37 as a second wiring layer is formed, and the surface is leveled with a silicon nitride film 38 remaining after etching.

Finally, a protective film 39 is formed on the surface as shown in FIG. 1(n).

Note that in FIG. 1 (j and <a), 40.41 is a resist coated on the silicon nitride film 36.38.

(Effects of the Invention) As described above, according to the method of the present invention, the surface can always be made flat by the insulating film remaining after etching, and it is possible to make the surface of the insulating film flat after etching. It is possible to stack up. By forming the connection layer separately from the wiring layer, it is possible to eliminate the difference in level at the connection part, and as a result, the thinning of the wiring can be eliminated and an increase in wiring resistance can be prevented. In order to have these effects, according to the method of the present invention, as shown in FIG. section), and interlayer free connections (sections 43 and 44) can be made easily.

[Brief explanation of drawings]

(Drawings) FIG. 1 is a cross-sectional view showing an example of the method for forming multilayer wiring of the present invention, FIG. 2 is a cross-sectional view showing an example of the multilayer wiring structure obtained by the method of the present invention, and FIG. FIG. 2 is a cross-sectional view showing a multilayer wiring structure obtained by a conventional method. 27...11%, 28...A/membrane 9 turns, 29
...Silicon nitride film, 30...Resist, 31...
・AI! l1g, 32... silicon nitride film, 33...
・Resist, 34...AI! Film pattern, 35...
AI! ! Pattern, 36... Silicon nitride film, 37.
...A/membrane turn, 38...silicon nitride film, 4
0.41...Resist. Honshimei-(combined・)/) Cross-sectional view 1 Figure 1
Picture book Motoaki - Soukata Sei row cqt map 1st section

Claims (1)

[Claims] (a) a step of forming a metal film on the entire surface; (b) a step of patterning the metal film; (c) a step of forming an insulating film on the entire surface including the metal film pattern; (d) etching the insulating film until the surface of the metal film pattern is exposed; and (e) repeating a series of steps for each wiring layer or connection layer to form a multilayer wiring. A method for forming multilayer wiring characterized by: