JPS62263671A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPS62263671A JPS62263671A JP10704886A JP10704886A JPS62263671A JP S62263671 A JPS62263671 A JP S62263671A JP 10704886 A JP10704886 A JP 10704886A JP 10704886 A JP10704886 A JP 10704886A JP S62263671 A JPS62263671 A JP S62263671A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- bipolar
- block
- wiring
- circuit block
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 12
- 238000009792 diffusion process Methods 0.000 abstract description 2
- 239000002184 metal Substances 0.000 abstract description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 2
- 229920005591 polysilicon Polymers 0.000 abstract description 2
- 230000010354 integration Effects 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000000644 propagated effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は半導体集積回路、特に規模が大きくて、回路ブ
ロック間の信号伝播遅延が大きくなる場合の回路構成に
関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor integrated circuit, and particularly to a circuit configuration that is large in scale and has a large signal propagation delay between circuit blocks.
従来の技術
従来のＭＯ８集積回路では、内部の回路が全てＭＯＳで
構成されていた。この方式では、ブロック間の信号伝播
速度を上げるため、信号線のプリチャージを行なう等の
方法が考案されている。最近では、ＭＯＳとバイポーラ
の混載させ、論理ゲートのドライブ側トランジスタをバ
イポーラで、負荷側ｉＭｏＳで実現する方法も考案され
ている。BACKGROUND OF THE INVENTION In a conventional MO8 integrated circuit, all internal circuits were composed of MOS. In this method, methods such as precharging signal lines have been devised to increase the signal propagation speed between blocks. Recently, a method has been devised in which MOS and bipolar are mixed, and the drive side transistor of the logic gate is made of bipolar, and the load side is made of iMoS.
発明が解決しようとする問題点
従来のように、チップ内部を全てＭＯＳで実現する方法
では、プリチャージ等の技術を使ったとしても高速化に
限界があった。又、ＭＯＳとバイポーラを混載させる方
法では、消費電流が非常に大きくなったり、回路の集積
度が低下したりする等の弊害があった。Problems to be Solved by the Invention In the conventional method of realizing the inside of a chip entirely using MOS, there was a limit to speeding up even if techniques such as precharging were used. Further, the method of mounting MOS and bipolar in a mixed manner has disadvantages such as extremely large current consumption and a decrease in the degree of circuit integration.
本発明は、回路の集積度を大巾に低下させたり、消費電
流を大巾に増加させることなく、回路の高速動作全実現
するととを目的とする。An object of the present invention is to fully realize high-speed operation of a circuit without significantly reducing the degree of integration of the circuit or significantly increasing current consumption.
問題点を解決するだめの手段
本発明は、複数個の回路ブロック及びｌ１０（入力又は
出力）セルによって構成される半導体集積回路において
、回路ブロック内−１ＭＯｓ回路によって構成し、他の
回路ブロック又はＩ１０セルとの間の信号線は、バイポ
ーラ回路によって駆動することを特徴とする半導体集積
回路である。Means for Solving the Problems The present invention provides a semiconductor integrated circuit constituted by a plurality of circuit blocks and I10 (input or output) cells. The semiconductor integrated circuit is characterized in that the signal line between the cell and the cell is driven by a bipolar circuit.
作 用
本発明によれば、回路の集積度を大巾に低下させたり、
消費電流を大巾に増加させることなく、回路の高速動作
を実現することが可能となる。Effects According to the present invention, the degree of integration of the circuit can be greatly reduced,
It becomes possible to realize high-speed operation of the circuit without significantly increasing current consumption.
実施例
以下、本発明の一実施例を添付図面にもとづいて説明す
る。Embodiment Hereinafter, one embodiment of the present invention will be described based on the accompanying drawings.
第１図は本発明の一実施例の平面図である。第１図にお
いて１は回路ブロック、２はＩ１０セル、３はバイポー
ラ回路、４はブロック間配線である。FIG. 1 is a plan view of one embodiment of the present invention. In FIG. 1, 1 is a circuit block, 2 is an I10 cell, 3 is a bipolar circuit, and 4 is inter-block wiring.
各回路ブロック１の内部ロジックはＭＯ８回路によって
構成されており、同回路ブロック１から他の回路ブロッ
ク１又はＩ１０セル２への信号の伝播を行なう部分では
、回路ブロック１から出た信号線が比較的回路ブロック
１から近い所でバイポーラ回路３の入力端子に接続し、
同バイポーラ回路３の出力端子側に他の回路ブロック１
又はＩ１０セル２へ接続する比較的長い配線が接続する
。The internal logic of each circuit block 1 is composed of MO8 circuits, and in the part where signals are propagated from the same circuit block 1 to other circuit blocks 1 or I10 cells 2, the signal lines coming out of circuit block 1 are Connect to the input terminal of the bipolar circuit 3 near the target circuit block 1,
Another circuit block 1 is placed on the output terminal side of the same bipolar circuit 3.
Alternatively, a relatively long wiring connected to the I10 cell 2 is connected.
半導体集積回路上で、回路ブロック１以外の部分すなわ
ちブロック間配線領域は拡散領域が使用されないのでバ
イポーラ回路の構成が可能である。On the semiconductor integrated circuit, no diffusion region is used in the portion other than the circuit block 1, that is, in the inter-block wiring region, so a bipolar circuit can be configured.
更にバイポーラ回路上で、配線とのコンタクトラとる部
分以外はポリシリコン又はメタル配線を引くことが可能
である。このため、ブロック間配線領域を使ってバイポ
ーラ回路及び配線を実現することにより、ＭＯＳのみで
回路を実現する場合とほぼ同等の集積度が得られる。Furthermore, it is possible to run polysilicon or metal wiring on the bipolar circuit except for the portions where contact with the wiring is made. Therefore, by realizing a bipolar circuit and wiring using the inter-block wiring area, it is possible to obtain almost the same degree of integration as when realizing the circuit using only MOS.
第２図は、本発明の一実施例の回路ブロック図である。FIG. 2 is a circuit block diagram of an embodiment of the present invention.
第２図において６はＭＯＳ）ランジスタである。大きな
容量を持つブロック間配線４とＭＯＳによって構成され
た回路ブロック１の出力端子の間にバイポーラ回路３を
設け、ブロック間配線４の充放電を高速に行なえるよう
にしている。In FIG. 2, 6 is a MOS transistor. A bipolar circuit 3 is provided between the interblock wiring 4 having a large capacity and the output terminal of the circuit block 1 constituted by MOS, so that the interblock wiring 4 can be charged and discharged at high speed.
発明の効果
本発明は、半導体集積回路において、集積度をほとんど
低下させることなく、回路の高速動作を得る効果がある
。Effects of the Invention The present invention has the effect of obtaining high-speed operation of a semiconductor integrated circuit without substantially reducing the degree of integration.
第１図は本発明の一実施例の半導体集積回路の概略平面
図、第２図は同半導体集積回路の回路図である。
１・・・−・・回路ブロック、３・・・・・バイポーラ
回路、４・・・・・・ブロック間配線、６・・・・・・
ＭＯＳ）ランジスタ。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名／−
−−回路、ブロック
２−一一工１０ ’ｃル
３−一一パイボーラ凹込
第 １ 図 ４−一−プロ
・ツクｒ！西已珠一１＝＝［＝＝］］FIG. 1 is a schematic plan view of a semiconductor integrated circuit according to an embodiment of the present invention, and FIG. 2 is a circuit diagram of the semiconductor integrated circuit. 1...-Circuit block, 3...Bipolar circuit, 4...Inter-block wiring, 6...
MOS) transistor. Name of agent: Patent attorney Toshio Nakao and 1 other person/-
--Circuit, Block 2-11 Work 10 'cl 3-11 Pibora recess No. 1 Figure 4-1-Pro Tsukr! Juichi Nishimi 1==[==]]
Claims (2)
って構成される半導体集積回路において、前記回路ブロ
ック内をＭＯＳ回路によって構成し、他の前記回路ブロ
ック又は前記セルとの間の信号線は、バイポーラ回路に
よって駆動することを特徴とする半導体集積回路。(1) In a semiconductor integrated circuit constituted by a plurality of circuit blocks and input or output cells, the circuit block is constituted by a MOS circuit, and the signal lines between it and other circuit blocks or cells are bipolar. A semiconductor integrated circuit characterized by being driven by a circuit.
路を、回路ブロック間配線領域に配置することを特徴と
する特許請求の範囲第１項記載の半導体集積回路。(2) The semiconductor integrated circuit according to claim 1, wherein a bipolar circuit for driving signals of wiring between circuit blocks is arranged in a wiring area between circuit blocks.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10704886A JPS62263671A (en) | 1986-05-09 | 1986-05-09 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10704886A JPS62263671A (en) | 1986-05-09 | 1986-05-09 | Semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62263671A true JPS62263671A (en) | 1987-11-16 |
Family
ID=14449194
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10704886A Pending JPS62263671A (en) | 1986-05-09 | 1986-05-09 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62263671A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5101258A (en) * | 1989-02-09 | 1992-03-31 | Sony Corporation | Semiconductor integrated circuit device of master slice approach |
-
1986
- 1986-05-09 JP JP10704886A patent/JPS62263671A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5101258A (en) * | 1989-02-09 | 1992-03-31 | Sony Corporation | Semiconductor integrated circuit device of master slice approach |
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