JPS62257598A - Traffic signal controller - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] <Field of invention> The present invention relates to a traffic signal controller.

<Prior art and its problems> The red signal output circuit in the conventional traffic signal controller is
As shown in the figure.

In FIG. 2, reference numeral 11 denotes a decoder that outputs a staircase signal for each staircase from "1" to "n+1" and a ROM (read-only memory), D, which sets the display time of each staircase.
, , D is a diode, Vcc is a DC power supply, R+ ,
Rz is a pull amplifier resistance, INV2゜INV is an inverter (NOT element), N0RI is a NOR gate, B,
, 133. B is a buffer. Decoder, RO
The part surrounded by the chain line other than MII is the red signal output circuit 12
It is.

Next, the operation of this conventional example will be explained.

In principle, the terminals of all the stairs “l” to “n+1” are
It is at H level.

(2) When only the output stage "1" terminal of the green signal S is brought to the "L" level, the diode D1 becomes m111 and the diode D2 becomes non-conductive. Therefore, the input terminal of the inverter INV becomes "L" level, and its output terminal becomes "1B level." The "H" level output of this inverter INV2 is the buffer B,
Via Green Light S.

This signal is output to the green signal lamp, and the green signal lamp turns on.

On the other hand, since the input terminal of the inverter INV is at the "H" level, its output terminal is at the "L" level. Therefore, there is no output of the yellow signal SV via the buffer B. Furthermore, since the output terminal of the inverter INV is at the "11" level and the output terminal of the inverter INv is at the 'L' level, the output terminal of the NOR gate N0R1 is at the 'L' level, and the There is also no output of the red signal S5, that is, the yellow signal lamp and the red signal lamp are turned off.

The state in which the blue No. 11 lamp is turned on and the yellow and red signal lamps are turned off continues for the time period of the tier "1" when the terminal of the tier "1" is at the "L" level.

(2) When only the output stage "2" terminal of the yellow signal Sv is brought to the "L" level, the diode D2 becomes conductive and the diode D1 becomes non-conductive. Therefore, the input terminal of the inverter INV3 becomes "L" level, and its output terminal becomes "H2 level".
It is output as a yellow signal SV to the yellow signal lamp device, and the yellow signal lamp turns on.

On the other hand, since the input terminal of the inverter INV2 is at the "H" level, its output terminal is at the "L" level. Therefore, there is no output of the green signal S through the buffer B4.
Also, since the output terminal of inverter INV2 is at "L" level and the output terminal of inverter IN is at MH3 level, the output terminal of NOR (N○R game) is at "L" level, and the There is no output of the red signal S, that is, the green signal lamp and the red signal lamp are turned off.

The state in which the yellow signal lamp is turned on and the green signal lamp and the red signal lamp are turned off continues for the time period of the stage "2" when the terminal of the stage "2" is set to the "L° level".

■ At output stage "3" of red light S, all stages "l" to "H+l"
” terminal to return to “H° level.”

Then, both diodes D, , D become non-conductive, and the input terminals of both inverters rNVx and INVz become 1H.
level, and each output terminal becomes "L" level. Therefore, both of the two input terminals of the NOR gate NOR, become "L" level, and its output terminal becomes "H" level. The "H" level output of this NOR gate N0R1 is outputted as a red signal S to the red signal lamp via the buffer B, and the red signal lamp turns on.

On the other hand, as mentioned above, since the output terminals of both inverters INV, , INV, are at "L" level, buffers B, , B
There is no output of the green signal S and the yellow signal Sv via s, ie the green signal lamp and the yellow signal lamp are turned off.

When the red signal lamp is turned on and the green signal lamp and yellow signal lamp are turned off, the terminals of all stairs “l” to “n+1” are “
It continues for the time of step "3" which is considered to be H° level.

The same applies to the stairs "4" to "n+1".

However, in this conventional traffic signal controller, the time of each stage "l" to "fi+l" is determined by a decoder.

Since it is fixedly determined in ROMI+ and outputs red data that is fixedly set for each staircase, it is not possible to arbitrarily change the light color display time regardless of the staircase, and furthermore, Stairs "1'~"fi+l"
Since the order is fixed, the order of lighting of the green signal lamp - lighting of the yellow signal lamp - lighting of the red signal lamp is fixed. Therefore, train interlocking control or train interlocking control,
There is a problem in that it is not possible to arbitrarily change the lighting order, which is necessary for special traffic signal control such as phase control.

<Object of the Invention> The present invention has been made in view of the above circumstances, and an object of the present invention is to enable the lighting time and lighting order of a plurality of lamps to be arbitrarily changed.

<Structure and Effects of the Invention> [Structure] In order to achieve the above object, the present invention has the following structure.

That is, the traffic signal side i1m device of the present invention includes: a fixed light color signal output means in which a ladder for a plurality of light devices whose lighting states are different from each other is fixedly set; variable light color signal output means for arbitrarily updating and setting the lighting time and lighting order; a state of output from the fixed light color signal output means to the plurality of lamps; and a state of output from the variable light color signal output means to the plurality of lamps. and output state switching means for switching between the output state and the output state to the lamp device.

[Effect]

The effects of this configuration are as follows.

When performing normal traffic signal control, a light color signal from a fixed light color signal output means corresponding to the normal traffic signal control is used. That is, the output state switching means sets a state in which the light color signal of the fixed light color signal output means is outputted to a plurality of lamps.

Furthermore, if the normal traffic signal 13 control cannot be used due to changes in traffic conditions, traffic signal control is performed using the light color signal from the variable light color signal output means. That is, the output state switching means sets a state in which the light color signal of the variable light color signal output means is outputted to a plurality of lamp devices.

In this case, the variable light color signal output means can arbitrarily change the lighting time and lighting order of the plurality of lamps, and the light color signal from the variable light color signal output means can be adjusted according to traffic conditions. Output the corresponding one.

〔effect〕

From the above, according to the present invention, the following effects are exhibited.

(a) Normal traffic No. 13 control using the output of the fixed light color signal output means, train interlock control using the output of the variable light color signal output means, train interlock control, phase, depending on the traffic situation. It is possible to switch between special traffic signal control and the like. When using the output of the variable light color signal output means, the lighting time and lighting order of multiple lamps can be set arbitrarily, making it possible to quickly and easily respond to changes in traffic conditions. Can be done.

(b) In addition, if the traffic signal control method is fundamentally changed, the lighting time and lighting order corresponding to the new method can be updated and set in the variable light color signal output means, so the method can be changed. can be easily dealt with.

<Description of Examples> Examples of the present invention will be described in detail below based on the drawings.

Fig. 1 shows the traffic signal side according to the embodiment of the present invention? 11n is a circuit diagram.

In Figure 1, 3 is a ROM (read-only memory) in which the light color data for each staircase is fixedly set.
, 4 is an IC (integrated circuit) that controls the ROM 3, and 5 is a lamp color signal output circuit having the same circuit configuration as the conventional red signal output circuit 12, and these are the fixed lamp color according to the configuration of the invention. It constitutes a signal output means 1.

6 is a CPU (central processing bag T1.) in the microcomputer, 7 is a ROM that stores a program for operating the CPLI 6, and 8 is a keyboard for manually setting the lighting time and lighting order of multiple lamps. 9 is a RAM (Random Access Memory) that stores the input lighting time 1 lighting order data, and these constitute the variable lamp color signal output means 2 according to the configuration of the invention. ing.

A N D + ~AND, is an AND gate, OR, ~O
R, is an OR gate, INV is an inverter, FF1 to F
F, is a clocked flip-flop, and B, ~B, are buffers.

As described above, the lamp color No. 13 output circuit 5 has the same circuit configuration as the lamp color signal output circuit 12 shown in FIG. The l input terminal of the AND gate AND, is connected to the blue signal output line I! of the light color signal output circuit 5. 1 is connected. AND gate A
The blue signal output line L1 of the CPLI 6 is connected to the 1 input terminal of N D z.

The yellow signal output line lt of the light color S output circuit 5 is connected to one input terminal of the AND gate AND. Δ
1 input terminal of ND game) AND, yellow of CPU6 (
No. 8 output lines L and t are connected. A red signal output line l of the lamp color signal output circuit 5 is connected to one input terminal of the AND gate ANDs. AND gate A
The red signal output line L of the CPU 6 is connected to one input terminal of N D b.

ANr) Gate AND, , to N D x , A N
The switching signal C3 is input to each of the other input terminals of the Ds via an inverter INV, and the switching signal C3 is input to the AND gate 8N, K, AND4,
A switching signal C8 is applied to each of the other input terminals of AND.
is configured to be input directly. The switching signal CS is for switching between the output state of the light color signal from the fixed light color signal output means 1 and the output state of the light color signal from the variable light color equal number output means 2. That is, when using the light color signal of the fixed light color No. 13 output means 1, set the switch A 3 CS to "L" level, and when using the light color signal of the variable light color signal output means 2. , sets the switching signal C3 to "H" level. .

The output terminals of the AND gates A N D + and A N D z are connected to the input terminals of the OR gate OR,
The output terminal of the gate is a flip-flop FF.

is connected to the input terminal of the A N D gate AN
The output terminals of Dff and AND are OR gates.

The output terminal of the OR gate 0Rffi is connected to the input terminal of the flip-flop FFz. The output terminals of the AND gates ANDS and AND& are connected to the input terminal of the OR gate OR3.
The output terminal of R4 is connected to the input terminal of flip-flop FF. Note that IO is a data selector, and this data selector 10 corresponds to the output state switching means in the configuration of the invention.

Flip-flop FF+, FF! , FFs are configured such that a trigger pulse TP is input to each clock input terminal T of the FFs. As this trigger pulse TP, when outputting a red signal from the fixed lamp color No. 13 output means 1, latch No. 13 of the ROM 3 is used, and when outputting a lamp color signal from the variable lamp color signal output means 2. The CP
The write signal of U6 is used.

Flip-flop F F + , F F z , F
A reset signal R3 is connected to each reset terminal RD of Fz.
is configured to be manually operated. This reset signal r? s is output when the power is turned on, and is also output by manual operation if necessary.

Flip-flop F F+ , F Fz , F F
3 each.

Output terminal Q tri, buffer B+, Bz respectively
, B3, and its output terminals are connected to a green signal lamp, a yellow signal lamp, and a red signal lamp, respectively.

〃L two works Next, the operation of this embodiment will be explained.

■ When the output power is turned on from the fixed lamp color signal output means 1, the reset signal R3 is output, and the flip-flop F
F+ to F F z are reset. “When the L° level switching signal C5 is output, the AND gate A N D2
, A N Da , A N Da becomes a non-dedicated state, and “■1” is inverted by the inverter I NV.
“There is a level of human power in ND game LANDI, A
ND, , AND become conductive.

As in the case of the conventional example, at step "1", the ROM
3 to "II" level blue data Dos is output to the AND gate AND. Therefore, the AND gate AND
, becomes conductive, and blue data D1□ is outputted to the input terminal of the flip-flop FF via the OR gate OR.

At the timing when the trigger pulse TP outputted from IC4 as a latch signal of ROM3 is inputted to the clock terminal T of the flip-flop FF, blue data DI11 is outputted from the output terminal Q, and the blue signal SR is outputted via the buffer B1.
It is output to the green signal lamp as a green signal.

At the stage "2", the high level yellow data [)+y from ROM3 is output to the AND gate A N D 3. Therefore, the AND gate A N D 3 is conductive;
Yellow data DIY is output to the input terminal of flip-flop FF2 via OR gate ORt.

At the timing when the trigger pulse TP output from IC4 is input to the clock terminal T of the flip-flop FF, yellow data DIV is output from the output terminal Q, and is output to the yellow signal light device as a yellow signal SV via the buffer B2. Ru.

At stage "3", red data DIR of "■(" level) is outputted from the ROM 3 to the AND gate AND.

Therefore, AND game) A N D s conducts, and OR
Red data DI11 is output to the input terminal of flip-flop FF3 via gate OR1.

At the timing when the trigger pulse TP output from IC4 is input to the clock terminal T of the flip-flop FF, red data DI11 is output from the output terminal Q, and is sent as a red signal S to the red light lamp via the buffer B. is output to.

■ Output from the variable light color signal output means 2 When the power is turned on, the reset signal R5 is output, and the flip-flop F
F + ”'-F F * is reset. “H”
When the level switching signal C8 is output, the inverter INV
, the AND gates ANDI, AND3゜AND s with the input of "L" inverted by , become non-conductive, and the AND gates AND2, AND4
, ANDb becomes conductive.

CP tJ 6 to “)I” level blue data [)is
is output to the AND gate ANDz, then
AND game) ANDA becomes conductive, and blue data D is sent to the input terminal of flip-flop FF via ○R gate OR.
, is output. At the timing when the write signal from the CPL 16 is input as a trigger pulse TP to the clock terminal T of the flip-flop FF, blue data I) za is output from the output terminal Q, and the blue signal S is output via the buffer B1, and then the blue signal 1δ is output. Output to the signal light device.

Yellow data of "■1" level from CPU6 I) zv is AN
When it is output to the D gate AND4, the AND gate AND becomes conductive, and the yellow data D27 is output to the input terminal of the flip-flop FF2 via the OR gate OR2. At the timing when the trigger pulse TP from the CPU 6 is input to the clock terminal T of the flip-flop FF, the yellow data I)zv is output from the output terminal Q, and is output to the yellow signal light device as the yellow signal S7 via the buffer B2. Ru.

When the red data D21 at "H° level" is output from the CPU 6 to the AND gate 1-AND, the AND gate A
ND becomes conductive, and red data D21 is outputted to the input terminal of the flip-flop FFs via the OR gate 0Rff. At the timing when the trigger pulse 'rP from the CPU 6 is input to the clock terminal T of the flip-flop FF, red data D21 is output from the output terminal Q, and is sent to the red signal S via the buffer B and then to the red light lamp. Output.

Blue data D above! , 5 yellow data D27. Red data Dt
The output time of * and the order of output 1 follow the program stored in RAM 9. The program can be changed by manual input means 8.

In other words, a program with arbitrary output time and output order can be RA
It can be stored in M9. Therefore, green light equipment,
It is possible to arbitrarily control the lighting time and lighting order of the yellow and red signal lamps.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a traffic signal controller according to an embodiment of the present invention, and FIG. 2 is a circuit diagram of a lamp color signal output circuit in a conventional traffic signal controller. l...Fixed light color signal output means 2...Variable light color signal output means 3...I20M, 5...Light color signal output circuit 6...
CPU, 8...Manual input means 9...RAM

Claims (1)

[Claims] (1) A fixed light color signal output means in which a ladder for a plurality of lamps with different lighting states is fixedly set, and lighting time and lighting order of the plurality of lamps are arbitrarily updated and set. a variable light color signal output means for switching between a state in which the fixed light color signal output means outputs to the plurality of lamp devices and a state in which the variable light color signal output means outputs to the plurality of light devices; A traffic signal controller equipped with an output state switching means.