JPS62254690A - Commutation failure detection system in inverter - Google Patents

Abstract

PURPOSE:To prevent a failure due to an overcurrent by comparing a bit pattern from a memory with a bit pattern detected through a switching element fired actually to detect the commutation failure of an inverter. CONSTITUTION:A current vector phase detector 11 inputs output phase currents iv, iw to bit-pattern current vector phases and outputs them. A memory 12 stores bit patterns of each current vector phase by obtaining them in advance. A comparator 13 compares a bit pattern from the memory 12 with the bit pattern from the detector 11 to judge that it is normal when both are coincident with each other and it is judged as commutation failure when both are not coincident.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application] The present invention relates to an inverter device for driving an alternating current machine such as an induction motor, and particularly to a commutation failure detection method thereof.

[Conventional technology]

FIG. 5 is a schematic diagram showing a general example of a motor drive system using an inverter.

That is, the inverter consists of a control device 1% forward converter 2 and an inverse converter 3, and by controlling the starting of the forward converter 2 and the inverse converter 30 by the control device 1, desired AC power is transferred to the AC converter 4. It is intended to supply

By the way, as a method for detecting commutation failure in such an inverter, for example, the method shown in FIG. 6 is known.

In the figure, 15 (15a, 15b) is a three-phase current detector including a rectifier, 16 (16a to 16c) is a comparator, 17 is an AND gate, and 18 is an interlock circuit.

This is done by detecting the three-phase combined input current by forward converting with the three-phase current detector 15a, and comparing it with a predetermined set value by the comparator 16a to determine the presence or absence of input current. 3 from the output current jutjw of the device 3 by the detector 15b and the comparator 16b.
determines whether there is a combined output current of the phase, and leads a signal indicating the presence or absence of the combined current of these inputs and outputs to the AND gate 17;
Commutation failure is detected from the output. In other words,
If the input current and output current match, it is considered normal, and if they do not match, it is assumed that a commutation failure has occurred. In addition, since there is a risk of erroneous determination at low speeds, the speed signal n from a speed detection means such as the pulse generator 5 in FIG. The inter-four circuit 18 is activated.

[Problem that the invention seeks to solve]

However, in the above-mentioned method, a failure is determined only by the presence or absence of current, so even if a commutation failure occurs, it cannot be detected as long as the failure current is flowing through the motor. That is, since an overcurrent state is detected only after commutation failure occurs, there is a problem that not only is there a delay in detection, but also that the cause of the failure cannot be accurately determined. Furthermore, from the viewpoint of preventing malfunctions, when the rotational speed of the motor is low and the current value is small, there is a problem in that an interlock is applied and detection becomes impossible.

Therefore, it is an object of the present invention to quickly and accurately detect commutation failure regardless of the presence or absence of a fault current or the rotational speed of the motor.

[Means for solving problems]

a detection means for detecting the current vector; a memory for storing bit patterns for each phase of this current vector; A control means for determining and controlling the switching elements to be turned off is provided.

[Effect]

The switching element is turned on by the control means.

The bit pattern determined to be off is compared with the bit pattern actually detected by the detection means as a result of applying this pattern, and commutation failure is detected from the comparison result.

〔Example〕

FIG. 1 is a block diagram showing an embodiment of the present invention.

In the figure, 11 is a current vector phase detector, 12 is a memory, and 13 is a converter terminal.

The current vector phase detector 11 is composed of a conversion circuit 11a and an identification circuit 11b, and detects the current vector phase based on the motor stator shaft in a bit pattern from the output current of the inverter ('ue iW in the figure). That is, the conversion circuit 11a introduces an output phase current bow t iwt'' to find 1vt, and calculates each phase current F r 'y t '
y't' Motor stator fine component ia and component iβ perpendicular to this are converted into two axis components, and the discriminating circuit 11b uses these two components.
The current vector phase is converted into a bit pattern according to the magnitude and polarity of the axial component.

Figure 84 is for explaining the principle. Figure 2 is a block diagram showing an induction motor drive system using a current source inverter, Figure 3 is a vector diagram showing the motor-order current vector, and Figure 4. is 1! Minute of flow vector space 111J, 6
FIG.

That is, as shown in figure fli2, the thyristor T Hu~T
Current source inverter 3 with H2=i switching element
The primary current (line current FIt) of the induction motor 4 driven by
) is a fixed phrase position iu at every 6σ as shown in Figure 3.
z Nj yu (30°, 90°, 150°.

-150°, -90°, -30°). Therefore, if we keep this entire area (360° space), we will have boundaries ttALl, L2 . It is divided into six areas A1 to A6 by L3. Note that at this time, each boundary line is arranged so that the six current vector positions are exactly at the center of each area. In this way, the position of the current vector can be determined from these three boundaries 1st
- It can be distinguished by which side it is on when pinched. Therefore, by providing a boundary-specific circuit corresponding to each boundary line and giving logic 11" or '1" depending on which side the current vector exists, each identification circuit can output a unique signal corresponding to the region where the current vector exists. A bit pattern of is obtained, from which the current vector phase can be determined.

On the other hand, in the memory 12, bit patterns for each current vector phase obtained as described above are obtained and stored in advance. The comparator 13 compares the bit pattern from the memory 12 and the bit pattern from the detector 11, and if they match, it is normal; if they do not match, it is judged that a commutation failure has occurred. . In other words,
Since the switching element is selectively turned on or off based on the bit pattern actually detected by the detector 11 and the bit pattern from the memory 12, the bit pattern that determines whether to turn it on or off and the bit pattern given. By comparing the detected result with the bit pattern detected by the detector 11ft using the comparator 13, it is possible to determine whether or not the current is flowing through the correct route. At this time, if a temporal difference occurs between the two bit patterns given to the comparator 13, the adjustment can be made using a timer or the like (not shown).

In addition, in the above, the comparator 13 is replaced by the control device W! (See reference numeral 1 in FIG. 5) is provided as hardware, but it is also possible to process this using software of the control device. It goes without saying that the current vector phase detection device is not limited to the one described above, but any device that can determine the phase by converting it into a bit pattern may be used.

〔Effect of the invention〕

According to this invention, the bit pattern read from the memory and applied to the switching element is compared with the bit pattern detected via the switching element that is actually turned on based on this bit pattern, and the inverter is activated. Since a commutation failure is detected, (a) detection is performed accurately and quickly when a commutation failure occurs and fault current flows, and as a result, failures due to overcurrent can be prevented.

p) There is no need to apply an interlock based on the rotational speed to avoid false detection, and detection is possible even at startup or at low speeds.

Benefits such as:

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a block diagram showing an induction motor drive system using a current source inverter, and Fig. 3 is a vector diagram showing the motor-order current vector. Figure 4 is an explanatory diagram for explaining how the current vector space is divided, Figure 5 is a schematic diagram showing a general example of a motor drive system using an inverter, and Figure 6 is a conventional example of a commutation failure detection method. FIG. Description of symbols 1... Control device, 2... Forward converter (converter), 3... Inverse converter (inverter),
4... Alternating current machine (induction motor), 5... Pulse generator, 1109111. the law of nature! ≧It −J A
L M-h9sqai bllJ! l mi 11
＾ -11111 Flag opening circuit, llb...Identification circuit, 12...Memory, 13゜16 (16a
~16 c)・----・Comparator, 15 (15
a, 15b)...Three-phase current detector, 17...
...and gate, 18...inter four-way circuit. Agent Patent Attorney Akio Namiki Agent Patent Attorney Kiyoshi Matsuzaki - 1111111! ! 1 Koshirae 2 figure w3III β @4WJ

Claims (1)

[Claims] Detection means for detecting a current vector phase based on a motor stator shaft as a bit pattern from an output current of an inverter that drives an AC motor, and a bit pattern for each phase of the current vector is stored. and a control means that determines the next switching element to be turned off based on the bit pattern stored in the memory and the bit pattern detected by the detection means, and controls the switching element. The control means compares the bit pattern that determines arc extinction at the point of the switching element with the bit pattern that is actually detected by the detection means as a result of applying the pattern, and detects a commutation failure from the comparison result. A commutation failure detection method in an inverter characterized by detecting commutation failure.