JPS62254444A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS62254444A JPS62254444A JP9683086A JP9683086A JPS62254444A JP S62254444 A JPS62254444 A JP S62254444A JP 9683086 A JP9683086 A JP 9683086A JP 9683086 A JP9683086 A JP 9683086A JP S62254444 A JPS62254444 A JP S62254444A
- Authority
- JP
- Japan
- Prior art keywords
- film
- insulating film
- semiconductor substrate
- forming
- single crystal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 28
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 238000002955 isolation Methods 0.000 claims abstract description 30
- 238000000034 method Methods 0.000 claims abstract description 22
- 238000005530 etching Methods 0.000 claims abstract description 18
- 238000009792 diffusion process Methods 0.000 claims description 7
- 230000000295 complement effect Effects 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 30
- 229910052710 silicon Inorganic materials 0.000 abstract description 30
- 239000010703 silicon Substances 0.000 abstract description 30
- 239000013078 crystal Substances 0.000 abstract description 28
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 23
- 229910052814 silicon oxide Inorganic materials 0.000 description 23
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 13
- 229920005591 polysilicon Polymers 0.000 description 13
- 230000003647 oxidation Effects 0.000 description 6
- 238000007254 oxidation reaction Methods 0.000 description 6
- 229910052796 boron Inorganic materials 0.000 description 5
- 238000002513 implantation Methods 0.000 description 5
- 238000000926 separation method Methods 0.000 description 5
- -1 boron ions Chemical class 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
Landscapes
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
(産業上の利用分野)
本発明は、半導体装置の製造方法、特に半導体集積回路
における分離領域の形成に好適な製造方法に関するもの
である。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method suitable for forming isolation regions in a semiconductor integrated circuit.
(従来の技術)
半導体集積回路製造における分離領域の形成法としては
、従来、選択酸化法、接合分離法、トレンチ分離法1選
択的エピタキシャル成長法及び絶縁膜埋込み法等の様々
な技術が提案されているが。(Prior Art) Various techniques have been proposed as methods for forming isolation regions in semiconductor integrated circuit manufacturing, such as selective oxidation, junction isolation, trench isolation, selective epitaxial growth, and insulating film embedding. There is, though.
実用化されているものは選択酸化法と接合分離法程度で
ある。The only methods that have been put into practical use are the selective oxidation method and the junction isolation method.
(発明が解決しようとする問題点)
しかし、前記選択酸化法では、深い領域の分離、たとえ
ば、相補型MO8電界効果トランジスタのウェル領域の
分離が非常に難しく、他の設計的手段を講じなければな
らない、また前記接合分離法は、微細化が不可能である
。また、単に半導体基板に溝を形成し、その溝の内部に
絶縁膜を形成する前記トレンチ分離法では、溝底部にチ
ャネルストップ領域を形成することが非常に難しく、5
〜6p11の溝を形成する必要がある。また、分離領域
となる絶縁膜をあらかじめ形成しておき、素子領域にの
みエピタキシャル層を成長させる前記選択的エピタキシ
ャル成長法は、エピタキシャル成長中にファセットが生
じたり、結晶欠陥が発生するため実用化されていない、
また、半導体基板に1μ−程度の深さの傾斜をもった溝
を形成し、その溝の内部に絶縁膜を形成する前記絶縁膜
埋込み法も。(Problems to be Solved by the Invention) However, with the selective oxidation method, it is very difficult to isolate deep regions, for example, the well region of a complementary MO8 field effect transistor, and other design measures must be taken. Furthermore, the above-mentioned junction separation method cannot be miniaturized. Furthermore, in the trench isolation method, in which a trench is simply formed in a semiconductor substrate and an insulating film is formed inside the trench, it is extremely difficult to form a channel stop region at the bottom of the trench.
It is necessary to form a groove of ~6p11. In addition, the selective epitaxial growth method described above, in which an insulating film serving as an isolation region is formed in advance and an epitaxial layer is grown only in the element region, has not been put to practical use because facets and crystal defects occur during epitaxial growth. ,
There is also the insulating film embedding method, which involves forming an inclined groove with a depth of about 1 μm in a semiconductor substrate, and forming an insulating film inside the groove.
前記選択酸化法と同じように、深い領域の分離が殖しい
。As with the selective oxidation method, separation in deep regions is enhanced.
以上のように、従来の技術では、微細化を伴った深い領
域を分離することが非常に難しいという問題点があった
。As described above, the conventional technology has a problem in that it is very difficult to separate deep regions that are accompanied by miniaturization.
本発明は、分離領域の形成において深い領域の分離が可
能な半導体装置の製造方法を提供するものである。The present invention provides a method for manufacturing a semiconductor device that allows deep isolation in forming isolation regions.
(問題点を解決するための手段)
上記問題点を解決するために、本発明は、半導体基板面
上の分離領域となる部分に、この部分と同等もしくはそ
れより広い部分にあらかじめ第1の絶縁膜を形成してお
き、前記半導体基板面からのエピタキシャル成長及び前
記第1の絶縁膜上への横方向のエピタキシャル成長を施
すことにより、前記半導体基板全面にエピタキシャル層
を形成し、前記分離領域となる部分のエピタキシャル層
を開孔して前記開孔部に第2の絶縁膜を形成し、この絶
縁膜と前記第1の絶縁膜とにより分離領域を形成する。(Means for Solving the Problems) In order to solve the above problems, the present invention provides a method of first insulating a portion of a semiconductor substrate surface that will be an isolation region in advance in an area equal to or wider than this area. A film is formed in advance, and an epitaxial layer is formed on the entire surface of the semiconductor substrate by performing epitaxial growth from the surface of the semiconductor substrate and epitaxial growth in a lateral direction on the first insulating film, and forming a portion that will become the isolation region. A hole is opened in the epitaxial layer, a second insulating film is formed in the opening, and an isolation region is formed by this insulating film and the first insulating film.
従って、選択的エピタキシャル成長法に見られる結晶欠
陥の発生は、分離領域の底端部に限られるため1分離特
性が大幅に向上する。Therefore, the generation of crystal defects observed in the selective epitaxial growth method is limited to the bottom end of the isolation region, and the single isolation characteristics are greatly improved.
また、ウェル形成領域にあらかじめウェルと同じ型の不
純物をウェル濃度より1桁程濃く拡散しておき、分離後
にウェルの拡散を施せば、接合分離法と同等な特性が微
細パターンにおいて得られることになる。In addition, if the same type of impurity as the well is diffused into the well formation region in advance to a concentration of about one order of magnitude higher than the well concentration, and the well is diffused after separation, the same characteristics as the junction separation method can be obtained in fine patterns. Become.
(作 用)
本発明の製造方法によれば、エピタキシャル成長により
発生する絶縁界面における結晶欠陥層を大部分除去でき
、さらに、ウェル分離も微細パターンにより達成するこ
とができる。さらに、下地に絶縁膜が存在するために、
均一な深さの分離領域の形成が可能となり、従来、トレ
ンチ形成時に問題となっていた深さ方向の不均一性も解
消される。(Function) According to the manufacturing method of the present invention, most of the crystal defect layer at the insulating interface caused by epitaxial growth can be removed, and furthermore, well separation can be achieved using a fine pattern. Furthermore, due to the presence of an underlying insulating film,
It becomes possible to form isolation regions of uniform depth, and non-uniformity in the depth direction, which has conventionally been a problem when forming trenches, is also eliminated.
(実施例)
本発明の一実施例及び他の実施例を第1図及び第2図に
より説明する。(Example) One example and other examples of the present invention will be described with reference to FIGS. 1 and 2.
第1図及び第2図は本発明の半導体装置の製造方法の一
実施例及び他の実施例のそれぞれの工程を示す断面図で
、第1図(a)ないし第1図(i)及び第2図(a)な
いし第2図(Q)は、それらの工程順を示したものであ
る。1 and 2 are cross-sectional views showing steps of one embodiment and another embodiment of the method for manufacturing a semiconductor device according to the present invention, and FIGS. 1(a) to 1(i) and Figures 2(a) to 2(Q) show the order of these steps.
第1図及び第2図において、1はN型シリコン基板、2
,8.11は酸化シリコン膜、3.12は注入マスク、
4,13はボロンイオン、5,14はP型拡散層、6は
シリコン単結晶層、7はエツチングマスク、9.IQは
ポリシリコン膜、15は被分離工ピタキシャル層である
。In FIGS. 1 and 2, 1 is an N-type silicon substrate, 2
, 8.11 is a silicon oxide film, 3.12 is an implantation mask,
4 and 13 are boron ions, 5 and 14 are P-type diffusion layers, 6 is a silicon single crystal layer, 7 is an etching mask, and 9. IQ is a polysilicon film, and 15 is a pitaxial layer to be separated.
第1図(a)では、N型シリコン基板1上に熱酸化シリ
コン股を300nm成長させ、分離領域となる部分のみ
エツチングにより残し、間隔lOμ9幅2μの2個の酸
化シリコン膜2を形成し、第1の絶縁膜とした1次に第
1図(b)では、N型シリコン基板1上に850℃、
30Torrの低温、低圧のエピタキシャル成長により
厚さ3p園のN型シリコン基板1と同一導電型のシリコ
ン単結晶層6を形成した。In FIG. 1(a), a thermally oxidized silicon crotch is grown to a thickness of 300 nm on an N-type silicon substrate 1, and only the portion that will become the isolation region is left by etching, forming two silicon oxide films 2 with a distance of lOμ9 and a width of 2μ. In FIG. 1(b), the primary insulating film is heated at 850°C on the N-type silicon substrate 1.
A silicon single crystal layer 6 having a thickness of 3p and having the same conductivity type as the N-type silicon substrate 1 was formed by epitaxial growth at a low temperature and pressure of 30 Torr.
この時酸化シリコン膜2上へのシリコン単結晶層6の横
方向のエピタキシャル成長のため、酸化シリコン膜2の
上部では、シリコン単結晶層6にくぼみが生じた。次い
で第1図(c)では、分離領域を形成するため、シリコ
ン単結晶層6上に酸化シリコン膜2の幅より狭い1.6
μの開孔部をあけ、それ以外の部分にエツチングマスク
7を施し、第1図(d)に示すように1反応性イオンエ
ツチング法によりシリコン単結晶層6に、酸化シリコン
膜2に到達するまで異方性エツチングを施して除去した
。次に第1図(e)では、エツチングマスク7を除去し
た後、シリコン単結晶層6の表面に20゜n11の酸化
シリコン膜8を成長させて第2の絶縁膜の一部とした。At this time, due to the horizontal epitaxial growth of the silicon single crystal layer 6 on the silicon oxide film 2, a depression was formed in the silicon single crystal layer 6 above the silicon oxide film 2. Next, in FIG. 1(c), in order to form an isolation region, a layer of 1.6 mm narrower than the width of the silicon oxide film 2 is formed on the silicon single crystal layer 6.
An opening of μ is made, an etching mask 7 is applied to the other parts, and the silicon single crystal layer 6 is reached to the silicon oxide film 2 by one-reactive ion etching as shown in FIG. It was removed by anisotropic etching. Next, in FIG. 1(e), after removing the etching mask 7, a 20° n11 silicon oxide film 8 was grown on the surface of the silicon single crystal layer 6 to form a part of the second insulating film.
次に第1図(f)では、前記開孔部を充填するためにポ
リシリコン膜9を被着し、第1図(g)に示すように前
記開孔部に充填したポリシリコン膜10以外のポリシリ
コン膜9をエツチングにより除去した0次いで第1図(
h)では、ポリシリコン膜10上に厚さ400nmの酸
化シリコン膜11を熱酸化により形成したが、この時酸
化シリコン膜8の膜厚の増加は50n■以下であった。Next, in FIG. 1(f), a polysilicon film 9 is deposited to fill the opening, and as shown in FIG. 1(g), other than the polysilicon film 10 filled in the opening. After removing the polysilicon film 9 by etching, the polysilicon film 9 shown in FIG.
In h), a silicon oxide film 11 with a thickness of 400 nm was formed on the polysilicon film 10 by thermal oxidation, but the increase in the thickness of the silicon oxide film 8 at this time was less than 50 nm.
さらに第1図(i)に示すように、シリコン単結晶層6
上の酸化シリコンwX8を、シリコン単結晶層6の表面
が露出するまでエツチングして除去した。このようにし
て酸化シリコン膜8及び11とポリシリコン膜10を併
せて第2の絶縁膜とし、この第2の絶縁膜と前記第1の
絶縁膜とによって分離領域を形成し、この2個の前記分
離領域に挾れたエピタキシャル層の領域15が、残余の
エピタキシャル層の領域から分離されることになる。Further, as shown in FIG. 1(i), a silicon single crystal layer 6
The upper silicon oxide wX8 was removed by etching until the surface of the silicon single crystal layer 6 was exposed. In this way, the silicon oxide films 8 and 11 and the polysilicon film 10 are combined to form a second insulating film, and an isolation region is formed by this second insulating film and the first insulating film, and these two The region 15 of the epitaxial layer sandwiched between the isolation regions will be separated from the remaining regions of the epitaxial layer.
次に、第2図により本発明の他の実施例を説明する。Next, another embodiment of the present invention will be explained with reference to FIG.
第2図(a)では、N型シリコン基板1上に熱酸化シリ
コン膜を300nm成長させ1分離領域となる部分のみ
エツチングにより残し1間隔10μ9幅2μの2個の酸
化シリコン膜2を形成し、第1の絶縁膜とした。次に第
2図(b)では、N型シリコン基板1上に形成するP型
ウェル領域以外の領域を注入マスク3で覆い、ボロンイ
オンを注入し注入層4を形成した。第2図(c)では注
入層4に公知のアニール処理を施し、P型拡散層5に変
換した後、N型シリコン基板1上に850℃、 30T
orrの低温、低圧のエピタキシャル成長により厚さ3
p11のシリコン単結晶層6を形成した。この時、酸化
シリコン膜2上へのシリコン単結晶層6の横方向のエピ
タキシャル成長のため、酸化シリコン膜2の上部では、
シリコン単結晶層6にくぼみが生じた。In FIG. 2(a), a thermally oxidized silicon film is grown to a thickness of 300 nm on an N-type silicon substrate 1, and only the portion that will become one isolation region is left by etching to form two silicon oxide films 2 with an interval of 10 μ9 and a width of 2 μ. This was used as the first insulating film. Next, in FIG. 2(b), regions other than the P-type well region formed on the N-type silicon substrate 1 were covered with an implantation mask 3, and boron ions were implanted to form an implantation layer 4. In FIG. 2(c), the injection layer 4 is subjected to a known annealing process to convert it into a P-type diffusion layer 5, and then is placed on an N-type silicon substrate 1 at 850° C. for 30T.
Thickness 3 by low-temperature, low-pressure epitaxial growth
A silicon single crystal layer 6 of p11 was formed. At this time, due to the horizontal epitaxial growth of the silicon single crystal layer 6 on the silicon oxide film 2, on the upper part of the silicon oxide film 2,
A depression was formed in the silicon single crystal layer 6.
次いて第2図(d)では、分離領域を形成するため、シ
リコン単結晶層6上に酸化シリコン膜2の幅より狭い1
.6μの開孔部をあけ、それ以外の部分にエツチングマ
スク7を施し、第2図(e)に示すように1反応性イオ
ンエツチング法によりシリコン単結晶層6に、酸化シリ
コン膜2に到達するまで異方性エツチングを施して除去
した0次に第2図(f)では、エツチングマスク7を除
去した後、シリコン単結晶層6の表面に200n園の酸
化シリコン膜8を成長させて第2の絶縁膜の一部とした
0次に第2図(g)では前記開孔部を充填するためにポ
リシリコン膜9を被着し、第2図(h)に示すように前
記開孔部に充填したポリシリコン膜10以外のポリシリ
コン膜9をエツチングにより除去した。Next, in FIG. 2(d), in order to form an isolation region, a layer narrower than the width of the silicon oxide film 2 is placed on the silicon single crystal layer 6.
.. An opening of 6 μm is made, an etching mask 7 is applied to the other parts, and the silicon single crystal layer 6 is reached to the silicon oxide film 2 by one-reactive ion etching as shown in FIG. 2(e). In FIG. 2(f), after removing the etching mask 7, a silicon oxide film 8 with a thickness of 200 nm is grown on the surface of the silicon single crystal layer 6. In FIG. 2(g), a polysilicon film 9 is deposited to fill the opening, and as shown in FIG. 2(h), the opening is filled with polysilicon film 9. The polysilicon film 9 other than the polysilicon film 10 filled in was removed by etching.
次いで第2図(i)ではポリシリコン膜10上に厚さ4
00nmの酸化シリコン膜11を熱酸化により形成した
が、この時酸化シリコン膜8の膜厚の増加は50n−以
下であった。さらに第2図(j)に示すように、シリコ
ン単結晶層6上の酸化シリコン膜8に、シリコン単結晶
層6の表面が露出するまでエツチングを施して除去した
。このようにして酸化シリコン膜8及び11とポリシリ
コン@ioを併せて第2の絶縁膜とし、この第2の絶縁
膜と前記第1の絶縁膜とによって分離領域を形成した。Next, in FIG. 2(i), a film with a thickness of 4
A silicon oxide film 11 with a thickness of 00 nm was formed by thermal oxidation, but the increase in the thickness of the silicon oxide film 8 at this time was 50 nm or less. Furthermore, as shown in FIG. 2(j), the silicon oxide film 8 on the silicon single crystal layer 6 was etched and removed until the surface of the silicon single crystal layer 6 was exposed. In this way, the silicon oxide films 8 and 11 and the polysilicon @io were combined to form a second insulating film, and an isolation region was formed by this second insulating film and the first insulating film.
次いで第2図(k)に示すように、前記分離領域に挾れ
た領域にP型ウェル形成のため、前記分離領域を除いた
シリコン単結晶層6及び酸化シリコン膜11の表面に注
入マスク12を被覆した後、ボロンイオンを注入し注入
層13を形成した。最後に、第2図(12)に示すよう
に、注入マスク12を除去した後に、アニール工程及び
拡散工程によってP型拡散層14を形成した。Next, as shown in FIG. 2(k), in order to form a P-type well in the region between the isolation regions, an implantation mask 12 is applied to the surfaces of the silicon single crystal layer 6 and the silicon oxide film 11 excluding the isolation regions. After coating, boron ions were implanted to form an implanted layer 13. Finally, as shown in FIG. 2 (12), after removing the implantation mask 12, a P-type diffusion layer 14 was formed by an annealing process and a diffusion process.
なお1本発明の前記他の実施例では、P型゛ウェル形成
の場合についてのみ説明したが、本発明は。Note that in the other embodiments of the present invention, only the case of forming a P-type well has been described, but the present invention is similar to the above.
N型ウェルや両ウェル構造の場合にも使用できることは
当然である。It goes without saying that it can also be used in the case of an N-type well or a double-well structure.
(発明の効果)
以上のように、本発明の半導体装置の製造方法によれば
、分離領域の形成において微細化を伴った深い領域の分
離が可能となり、従って、集積回路の高密度化に著しい
効果を有する。(Effects of the Invention) As described above, according to the method of manufacturing a semiconductor device of the present invention, it is possible to isolate a deep region with miniaturization in the formation of an isolation region, and therefore, it is possible to significantly increase the density of integrated circuits. have an effect.
第1図は本発明の半導体装置の製造方法の一実施例の工
程を示す断面図、第2図は他の実施例の工程を示す断面
図である。
1・・・N型シリコン基板、2,8.11・・・酸化シ
リコン膜、3.12・・・注入マスク、4.13・・・
ボロンイオン注入層、5,14・・・P型拡散層、 6
・・・シリコン単結晶層、7・・・エツチングマスク、
9.10・・・ポリシリコン膜、 15・・・被分離エ
ピタキシャル層。
特許出願人 松下電子工業株式会社
第1図
第1図
第1図
第2図
4・・・ ボロン4オフ体入噛
第2図
第2図FIG. 1 is a sectional view showing steps in one embodiment of the method for manufacturing a semiconductor device of the present invention, and FIG. 2 is a sectional view showing steps in another embodiment. 1... N-type silicon substrate, 2, 8.11... Silicon oxide film, 3.12... Injection mask, 4.13...
Boron ion implantation layer, 5, 14...P type diffusion layer, 6
...Silicon single crystal layer, 7...Etching mask,
9.10...Polysilicon film, 15...Epitaxial layer to be separated. Patent applicant Matsushita Electronics Co., Ltd. Figure 1 Figure 1 Figure 1 Figure 2 Figure 4... Boron 4-off body interlocking Figure 2 Figure 2
Claims (2)
する2個の第1の絶縁膜を形成する第1の工程と、前記
第1の絶縁膜以外の前記半導体基板面からのエピタキシ
ャル成長および前記第1の絶縁膜上への横方向のエピタ
キシャル成長を施すことにより前記半導体基板全面に前
記半導体基板と同一導電型のエピタキシャル層を形成す
る第2の工程と、前記第1の絶縁膜上の前記第1の絶縁
膜幅と同等もしくはそれより狭い領域の前記エピタキシ
ャル層をエッチングにより除去し開孔する第3の工程と
、前記開孔部の公知の方法で第2の絶縁膜を形成する第
4の工程を具備することにより、前記第1の絶縁膜と前
記第2の絶縁膜とより成る前記の所定の間隔を有する2
個の分離領域を形成し、前記2個の分離領域間の前記エ
ピタキシャル層を残余の前記エピタキシャル層から分離
することを特徴とする半導体装置の製造方法。(1) A first step of forming two first insulating films having a predetermined interval and width on the surface of a semiconductor substrate of one conductivity type, and epitaxial growth from the surface of the semiconductor substrate other than the first insulating film. and a second step of forming an epitaxial layer of the same conductivity type as the semiconductor substrate on the entire surface of the semiconductor substrate by performing lateral epitaxial growth on the first insulating film; a third step of removing the epitaxial layer in a region equal to or narrower than the first insulating film width by etching to open a hole; and a second step of forming a second insulating film in the opening by a known method. By comprising the step 4, the second insulating film having the predetermined interval formed by the first insulating film and the second insulating film is formed.
1. A method of manufacturing a semiconductor device, comprising: forming two isolation regions, and separating the epitaxial layer between the two isolation regions from the remaining epitaxial layer.
する2個の第1の絶縁膜を形成する第1の工程と、前記
半導体基板上の前記2個の第1の絶縁膜間の領域に前記
半導体基板と逆導電型の拡散層を形成する第2の工程と
、前記第1の絶縁膜以外の前記半導体基板面からのエピ
タキシャル成長及び前記第1の絶縁膜上への横方向のエ
ピタキシャル成長を施すことにより前記半導体基板全面
に前記半導体基板と同一導電型のエピタキシャル層を形
成する第3の工程と、前記第1の絶縁膜上の前記第1の
絶縁膜幅と同等もしくはそれより狭い領域の前記エピタ
キシャル層をエッチングにより除去し開孔する第4の工
程と、前記開孔部に公知の方法で第2の絶縁膜を形成す
る第5の工程と、前記第1の絶縁膜と前記第2の絶縁膜
とより成る前記の所定間隔を有する2個の分離領域間の
前記エピタキシャル層に前記半導体基板と逆導電型の拡
散層を形成する第6の工程を具備することにより、相補
型MOSトランジスタのウェル領域を残余の前記エピタ
キシャル領域から分離することを特徴とする半導体装置
の製造方法。(2) A first step of forming two first insulating films having a predetermined interval and width on the surface of a semiconductor substrate of one conductivity type, and forming a gap between the two first insulating films on the semiconductor substrate. a second step of forming a diffusion layer of a conductivity type opposite to that of the semiconductor substrate in a region, epitaxial growth from the surface of the semiconductor substrate other than the first insulating film, and lateral growth on the first insulating film a third step of forming an epitaxial layer of the same conductivity type as the semiconductor substrate on the entire surface of the semiconductor substrate by performing epitaxial growth; and a third step of forming an epitaxial layer of the same conductivity type as the semiconductor substrate on the entire surface of the semiconductor substrate, and a width equal to or narrower than the width of the first insulating film on the first insulating film. a fourth step of removing the epitaxial layer in the region by etching to open a hole; a fifth step of forming a second insulating film in the opening by a known method; By comprising a sixth step of forming a diffusion layer of a conductivity type opposite to that of the semiconductor substrate in the epitaxial layer between the two isolation regions having the predetermined interval and consisting of a second insulating film, a complementary type A method for manufacturing a semiconductor device, comprising separating a well region of a MOS transistor from the remaining epitaxial region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9683086A JPS62254444A (en) | 1986-04-28 | 1986-04-28 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9683086A JPS62254444A (en) | 1986-04-28 | 1986-04-28 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62254444A true JPS62254444A (en) | 1987-11-06 |
Family
ID=14175461
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9683086A Pending JPS62254444A (en) | 1986-04-28 | 1986-04-28 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62254444A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5143862A (en) * | 1990-11-29 | 1992-09-01 | Texas Instruments Incorporated | SOI wafer fabrication by selective epitaxial growth |
| US5877065A (en) * | 1991-11-15 | 1999-03-02 | Analog Devices Incorporated | Process for fabricating insulation-filled deep trenches in semiconductor substrates |
| US6265691B1 (en) | 1996-11-05 | 2001-07-24 | Intermedics Inc. | Method of making implantable lead including laser wire stripping |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4914397A (en) * | 1972-05-31 | 1974-02-07 | ||
| JPS5854649A (en) * | 1981-09-28 | 1983-03-31 | Fujitsu Ltd | Manufacture of semiconductor device |
-
1986
- 1986-04-28 JP JP9683086A patent/JPS62254444A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4914397A (en) * | 1972-05-31 | 1974-02-07 | ||
| JPS5854649A (en) * | 1981-09-28 | 1983-03-31 | Fujitsu Ltd | Manufacture of semiconductor device |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5143862A (en) * | 1990-11-29 | 1992-09-01 | Texas Instruments Incorporated | SOI wafer fabrication by selective epitaxial growth |
| US5877065A (en) * | 1991-11-15 | 1999-03-02 | Analog Devices Incorporated | Process for fabricating insulation-filled deep trenches in semiconductor substrates |
| US6265691B1 (en) | 1996-11-05 | 2001-07-24 | Intermedics Inc. | Method of making implantable lead including laser wire stripping |
| US6326587B1 (en) | 1996-11-05 | 2001-12-04 | Intermedics Inc. | Apparatus for removing an insulating layer from a portion of a conductor |
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