JPS62242873A - Integrated circuit - Google Patents

Abstract

PURPOSE:To easily select a speed with high accuracy by utilizing the scan path of an FF which is normally utilized in an integrated circuit, converting this into a closed loop and oscillating it, and measuring its frequency. CONSTITUTION:Flip-flop (FF) circuits 2-1-2-normally receive a data input from a terminal DI and outputs it from a terminal DO in synchronism with a clock signal received through a terminal CLK. Further, when a test mode signal is inputted to a terminal TST through a NAND circuit 4, operation control by the clock signal is reset and a shift mode signal is supplied to a terminal SFM; and then the scan path is connected in series through the terminals DO and SI and enters a passage mode wherein the output data of a selector circuit 1 is passed. In a test mode state, a closed loop is formed by the circuit 1 so that the DO terminal output of the circuit 2-n is supplied to the terminal Si of the circuit 2-1 through a NAND circuit 3 and the circuit 1; and the scan path enters an oscillation stage based upon output forward feedback and then a propagation delay time is determined by measuring the oscillation frequency of the DO output of the circuit 2-n.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to integrated circuits, and more particularly to an improvement in the selection technique for integrated circuits having scan paths in which flip-flop circuits are serially connected.

[Conventional technology]

Flip-flop circuits are frequently used in integrated circuits as components of sequential circuits, timing circuits, or temporary data memory. The scan path formed by serially connecting these clip-flop circuits allows the 7-lip, 70-tub circuit to be observed from the test machine by passing data in a predetermined format through this scan path, and also allows the test data to be transmitted from the test machine. Since it can be directly set, it can be treated in the same way as an input/output terminal, making it possible to efficiently generate failure test data and execute failure tests for a single integrated circuit.

On the other hand, the propagation delay time can be measured by activating a specific path within the integrated circuit, and the propagation delay time characteristics can be divided into several groups based on not only individual performance but also variations in integrated circuit manufacturing. Select and capture. It is well known that so-called speed selection can be performed, and it is almost an indispensable selection technology when a large number of integrated circuits are used. The disadvantage is that it requires a lot of computer time.

[Problem that the invention seeks to solve]

The conventional integrated circuit speed selection process described above has a problem in that it becomes difficult to maintain high accuracy as integrated circuits become more highly integrated and faster.

To solve this problem, a method has recently been used in which a ring oscillation circuit or the like is mounted on a specific part such as the outer periphery of an integrated circuit and the variation in propagation delay time is represented based on the oscillation frequency. However, there is a problem in that the tendency of variation does not necessarily match the propagation delay time of the integrated circuit itself.

An object of the present invention is to eliminate the above-mentioned drawbacks, and to easily select the propagation velocity by making use of the serially connected scan paths of free-lag flop circuits commonly used in integrated circuits and bringing them into an oscillating state. The objective is to provide an integrated circuit that can be

[Means for solving problems]

The circuit of the present invention includes, in an integrated circuit having a scan path formed by serially connecting clip-crop circuits, a test mode setting means for setting a test mode in which test data can be passed through the scan path; and closed loop forming means for setting the flip-flop circuit to a pass mode when the test mode setting means sets the test drive mode on the scan path, and forming a closed loop circuit capable of oscillation on the scan path.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

The embodiment shown in FIG. 1 is comprised of a selector circuit 1, flip-flop circuits 2-1 to 2-n, NAND circuits 3.4, and the like.

The selector circuit 1 selects the output of the NAND1$ path 3 only when receiving a test mode signal from the outside such as the integrated circuit tester body via the NAND circuit 4ft, but in other so-called normal times, it selects the shift-in data and outputs the flip-flop. It is supplied to the SI terminal of the pull-up circuit 2-1. Furthermore, when receiving a shift mode signal from an external source such as the main body of an integrated circuit tester, each flip-flop circuit enters the shift mode.
-nKa As will be described later, a scan path is formed, and the scan path output based on the shift-in data is output from the flip-flop circuit 2-n as shift-at data. Furthermore, the output side of flip 70 tube 2-n is NAND
It is positively fed back to the flip-flop circuit 2-1 via the circuit 3 and the selector circuit 1 to form a closed loop and bring the scan path into an oscillating state.

In the normal state in which no shift mode signal is received, no scan path is formed, so each flip-flop circuit receives data input from the DI terminal, and no closed loop is formed.

By the way, each of the flip-flop circuits 2-1 to 2-n normally operates in synchronization with a clock signal received via a CLK terminal, receives data input from a DI terminal, and sends out its output via a DO terminal. This is done on the unique operation of components within an integrated circuit.

In addition, the test mode signal T is transmitted via the NAND circuit 4.
8 When inputting to the 'I' terminal, the operation control by the clock signal is canceled, and at this time, when a shift mode signal is further supplied to the SMF5@ child, they are serially connected to each other via the 80 and 81 terminals to form a scan path. A pass mode is established in which the output data of the selector circuit 1 is passed through this scan path instead of inputting data. Furthermore, in this test mode state, the selector circuit 1 forms a closed loop so that the DO terminal output of the flip-flop circuit 2-n is provided to the 8I terminal of the flip-flop circuit 2-1 via the NAND circuit 3 and the selector circuit 1. The scan path thus formed into a closed loop circuit enters a firing state due to positive output feedback.

In this state, when the oscillation local wave a/ at the DO ratio output of the flip-flop circuit 2-n is measured, the propagation delay time can be calculated from the value of f determined as the reciprocal of the propagation delay time '1' of the total 7-lip 70-tube circuit. Determined with high accuracy.

Note that the NAND circuit 3 is for providing positive feedback from the output side of the flip-flop circuit to the input side, and the NAND circuit 4 is for providing a test mode signal with the required polarity to each flip-flop circuit. Of these, the NAND circuit 4 may be unfavorable depending on the polarity of the test signal to be input to the flip-flop circuit.

Conventionally, a part of the functional circuit in the normal operation mode is activated by an activation pattern, and the difference between the rising edge/falling edge of the input waveform and the rising edge/falling edge of the output waveform is detected using a synchroscope, etc. Although the propagation delay speed is determined by observing the

FIG. 2 is a circuit diagram showing details of the flip-flop circuit in the embodiment of FIG. 1, j), NAND circuit 21.2
2.24.27.28. AND/NAND circuit 23,
It is configured to include a master latch circuit 25, a slave latch circuit 26, and the like.

These flip-flop circuits 2-1 to 2-n.

Normally, the clock signal received at the CLK terminal is the NAND circuit 2
It has two latch circuits, a mask latch circuit 25 and a slay latch circuit 26, each of which operates by being supplied to the C terminal through a NAND circuit 21 and a DI terminal. The signal is input to the I terminal of the circuit, and its output is supplied from the 0 terminal to the output terminal of the slay latch circuit 26, so that it is output in a predetermined output format from the DOC terminal.

The master latch circuit 25 and the slay latch circuit 26 have reciprocal hold states and through states for input signals, and are normally TNTs held at a "1" level.
For example, if the clock signal at the terminal input is a binary 'O'
, '1' level, when the master latch circuit 25 is at the '0' level, the master latch circuit 25 becomes a hold circuit that holds the human power up to the '1'level; conversely, the slay latch circuit 26
functions as a through circuit that outputs the input as is by the operation of the NAND circuit 28. Further, when the clock signal changes from the "O" level to the "1" level IC null, the master latch circuit 25 changes to a through circuit, and the slay latch circuit 26 changes to a hold circuit. In this way, when the slay latch circuit 26 changes from a hold circuit to a through circuit, the data input to the master latch circuit 25 is input to the DOC terminal at the timing when the clock signal falls from "1" to "0" until the level of the clock signal changes. Flip 70 that looks like it's coming out
Perform whelk processing.

Both the master latch circuit 25 and the slave latch circuit 26 can be basically constructed of the same circuit.

FIG. 3 is a circuit diagram showing the master latch circuit part of the flip-flop circuit in FIG. 2 in detail.
51, 253, 254 and ANL)/NAND circuit 252
It is composed of: Note that the AND/NAND circuit 25
2 is A that provides only output polarity or two outputs that are opposite to each other.
ND (or Nfi:JL) circuit is shown. Assuming that the black signal input from the CLK terminal is at "O" and "1" levels, # Q If the TS'l" terminal input is at "l" level when it is at N level, the C terminal will be at "1" level. In this case, the master latch circuit 25 operates as a through circuit that outputs the input from the I terminal to the output terminal OK until the clock signal becomes "1", while the slave latch circuit 26 operates as a hold circuit. When the signal next reaches the '1' level, it is supplied to the C terminal at the 'θ' level, the states of the hold and through circuits described above are reversed, and the flip 70 process described above is performed.

In such a normal flip 70 tube process.

The TNT inputs of the flip-flop circuits 2-1 to 2-n are “
If the primary KTST terminal input is set to the "0" level while it remains at the "1" level, the C terminals of the master latch circuit 25 and the slave latch circuit 26 do not reach the level of the clock signal, and both become "1". is supplied, and both the master latch circuit 25 and the slave latch circuit 26, which are made of the same combination of logic gates, are set to the through state.

That is, both the master latch circuit 25 and the slave latch circuit 26 are released from the control of the clock signal, and whether the input from the DI terminal or the input from the SI terminal is selected as an input is determined by inputting it to the S)'M terminal. This will be determined by the shift mode signal. This shift mode signal is passed through the ANL)/NAND circuit 23tl to N
By providing each of the AND circuits 21 and 22 as a single input, the input from the 9DI terminal is cut off, and only the input from the 8I terminal is supplied to the master 2-way circuit 25 via the NANL) circuit 24. In this way, the clip-flop circuits 2-1 to 2-n all accept the input from the SI terminal as L.
) It becomes possible to output to the 0 terminal. In this state, shift-in data is transferred from selector circuit 1 to flip-flop circuit 2.
-1 to the SI terminal of NANI) to set all flip-block circuits to serial connection state, and then connect the output of NANI) circuit 3 to flip-flop circuit 2-1 via selector circuit 1.
A closed loop circuit provided to the to8Iffi child is formed to force the scan path into an oscillation state. By measuring this oscillation frequency, the propagation delay time can be easily determined.

〔Effect of the invention〕

As explained above, according to the present invention, a scan canvas of 7 lips and 70 lips, which is normally used in an integrated circuit, is used, and 4L is converted into a closed loop. Another advantage is that it is possible to realize an integrated circuit that can easily carry out rapid axillary sorting with extremely high precision.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a circuit diagram showing details of the Noritsubu flop circuit in the embodiment of FIG. 1, and FIG. 3 is a master latch in the flip-flop circuit of FIG. 2. FIG. 2 is a circuit diagram showing a portion of the circuit in detail.

Claims (1)

[Claims] A test mode for setting a test mode in which test data can be passed through the scan path in an integrated circuit having a scan path formed by serially connecting flip-flop circuits. a setting means; and a closed loop forming means for setting the flip-flop circuit to a pass mode and forming a closed loop circuit capable of oscillation on the scan path when the test mode setting means sets the test mode to the scan path. An integrated circuit characterized by: