JPS6222455A - Thin film active device substrate - Google Patents

Thin film active device substrate

Info

Publication number
JPS6222455A
JPS6222455A JP60161248A JP16124885A JPS6222455A JP S6222455 A JPS6222455 A JP S6222455A JP 60161248 A JP60161248 A JP 60161248A JP 16124885 A JP16124885 A JP 16124885A JP S6222455 A JPS6222455 A JP S6222455A
Authority
JP
Japan
Prior art keywords
electrode
auxiliary wiring
thin film
film active
electrodes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP60161248A
Other languages
Japanese (ja)
Other versions
JP2655638B2 (en
Inventor
Nobuhiko Imashiro
信彦 今城
Ryujiro Muto
武藤 隆二郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AGC Inc
Original Assignee
Asahi Glass Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Asahi Glass Co Ltd filed Critical Asahi Glass Co Ltd
Priority to JP60161248A priority Critical patent/JP2655638B2/en
Publication of JPS6222455A publication Critical patent/JPS6222455A/en
Application granted granted Critical
Publication of JP2655638B2 publication Critical patent/JP2655638B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/1306Details
    • G02F1/1309Repairing; Testing
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/13624Active matrix addressed cells having more than one switching element per pixel
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/136259Repairing; Defects
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/136259Repairing; Defects
    • G02F1/136263Line defects
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/136259Repairing; Defects
    • G02F1/136268Switch defects

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Liquid Crystal (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To repair perfectly and easily defects of the display using thin film active elements such as TFTs, by forming auxiliary wiring electrically insulated between separated electrodes or forming a section not intentionally being contacted electrically, to cause the up and down conduction through the wiring or the section by laser. CONSTITUTION:After amorphous silicon oxide is formed on a glass substrate, an amorphous silicon layer is formed. After it is patterned, Al is evaporated, and patterning forms a source line 2, source electrodes 3, 4, drain electrodes 5, 6 and auxiliary wiring 11. An amorphous silicon oxide layer is formed thereon as an insulating film by plasma CVD and an Al layer is evaporated by EB evaporation. After patterning forms a gate line 7 and auxiliary wirings 9A, 9B, dry etching opens a contact hole 8. Thereafter, EB evaporation forms an ITO film, and a lift-off method patterns a display pixel electrode 10.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は多数の薄膜能動素子を行列電極の交差点近傍に
配置したtI膜能能動素子基板関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a tI film active element substrate in which a large number of thin film active elements are arranged near intersections of row and column electrodes.

[従来の技術] 最近OAa器端末やポータプルテレビ等への要求から薄
形ディスプレイ開発が盛んに行われている。その中でも
大容量グラフィック表示に対応するために行列状に電極
を配置した情報表示装置において、前記電極交差点部に
能動素子を配して駆動を行うアクティブマトリクス方式
が研究されている。第2図に薄膜能動素子としてfil
l15I)ランジスタ(以下TPTと略す)を用いた液
晶パネル形ディスプレイの概念図を示す、 (21)が
液晶層であり、(22)が前記液晶層を駆動するための
スイッチングトランジスタである。 (23)は液晶を
駆動するために必要な電圧を印加するためのデータ線で
あり、(20はトランジスタ(22)のゲートを制御す
る選択信号線である。 (25)及び(2B)は、透明
電極である。
[Prior Art] Recently, development of thin displays has been actively carried out due to demands for office automation equipment terminals, portable televisions, and the like. Among these, an active matrix system is being researched in which active elements are arranged at the intersections of the electrodes for driving in information display devices in which electrodes are arranged in rows and columns in order to accommodate large-capacity graphic displays. Figure 2 shows fil as a thin film active element.
(21) is a liquid crystal layer, and (22) is a switching transistor for driving the liquid crystal layer. (23) is a data line for applying the voltage necessary to drive the liquid crystal, and (20 is a selection signal line that controls the gate of the transistor (22). (25) and (2B) are It is a transparent electrode.

第3図に、従来より知られているコープレナ構造を有す
るTPTの平面図を示す0図中(1)は、アルモファス
シリコン等からなる半導体層を、(2)ハソースライン
を、(3)は各トランジスタのソース電極を示す、これ
らは、AI等の金属により形成されている。(5)はド
レイン電極でソース電極と同様にAI等の金属により形
成されている。(7)はゲートラインで、ソース電極と
同様にAI等の金属により形成されている。
FIG. 3 shows a plan view of a conventionally known TPT having a coplanar structure. indicates the source electrode of each transistor, which is made of metal such as AI. Reference numeral (5) denotes a drain electrode, which is made of metal such as AI, like the source electrode. Reference numeral (7) denotes a gate line, which is made of metal such as AI, like the source electrode.

(8)はコンタクトホールでソース電極(3)とゲート
ライン(7)を絶縁するための絶縁膜にあけられており
、ドレイン電極(5)と表示画素電極(10)とを接続
するためのものである。 (1G)は表示画素電極で、
 ITO,5n02等の透明導電膜により形成される。
The contact hole (8) is made in the insulating film to insulate the source electrode (3) and the gate line (7), and is used to connect the drain electrode (5) and the display pixel electrode (10). It is. (1G) is the display pixel electrode,
It is formed from a transparent conductive film such as ITO or 5n02.

又、各表示画素電極に2以上の薄膜能動素子を形成して
用いることもあり、例えばエレクトロクロミック表示素
子(E CD)では、その駆動に液晶表示素子(LCD
)に比して大電流を      i要するため、1画素
に2個のTPTを用いたりする。
In addition, two or more thin film active elements may be formed and used on each display pixel electrode. For example, in an electrochromic display element (ECD), a liquid crystal display element (LCD) is used for driving the electrochromic display element (ECD).
), two TPTs are used for one pixel.

[発明の解決しようとする問題点] 上記の様に、薄膜能動素子を用いる事で視認性の良い高
密度情報表示が可能となるが、1画素に少なくとも1個
の割合で薄膜能動素子が必要なため数多くの薄膜能動素
子を無欠陥で作る事は非常に困難な事である。
[Problems to be solved by the invention] As mentioned above, high-density information display with good visibility is possible by using thin film active elements, but at least one thin film active element is required for each pixel. Therefore, it is extremely difficult to produce a large number of thin film active devices without defects.

薄膜能動素子に起因する欠陥としては、電極間相互の短
絡、各電極の断線といった構造的欠陥や、薄膜能動素子
特性の不良といった欠陥等がある。
Defects caused by thin film active elements include structural defects such as short circuits between electrodes and disconnections between electrodes, and defects such as defects in thin film active element characteristics.

電極間相互の短絡は、電極間絶縁膜中の塵等の原因によ
り発生するが、短絡がある場合には、一方の電極の信号
が短絡点を通じて逃げてしまうために線欠陥等の表示欠
陥の原因となってしまう。
Mutual short circuits between electrodes occur due to dust in the interelectrode insulating film, but when there is a short circuit, the signal from one electrode escapes through the short circuit point, resulting in display defects such as line defects. It becomes the cause.

また薄膜能動素子の電気的特性が不良の場合には、信号
電圧が印加されても薄膜能動素子が充分な動作をしない
ために選択時に非点灯欠陥となる。
Furthermore, if the electrical characteristics of the thin film active element are poor, the thin film active element will not operate sufficiently even when a signal voltage is applied, resulting in a non-lighting defect when selected.

以上の様な欠陥の数は、製造プロセスの管理状態に、よ
り異なるが、表示品位として要求されるレベルでは、線
欠陥は1本も許されず、点欠陥としても、全画素の0.
01%以下にする必要があるが、現状としては、 20
0本以上のラインを持つ基板中では、 0〜数本のライ
ン欠陥や数個の点欠陥が含まれる事が多く、セルの歩留
りが低く、薄膜能動素子を用いた情報表示装置の実用化
を妨げる主な問題点となっていた。
The number of such defects as described above varies depending on the management status of the manufacturing process, but at the level required for display quality, not even a single line defect is allowed, and even a point defect is 0.
It is necessary to keep it below 0.1%, but currently it is 20.
Substrates with zero or more lines often contain zero to a few line defects or several point defects, resulting in low cell yields and impeding the practical use of information display devices using thin-film active elements. This was the main obstacle.

このような基板の欠陥の修復方法としては欠陥部位の切
断及び接続の2工程が必要となる。
A method for repairing such defects in a substrate requires two steps: cutting and connecting the defective portion.

切断方法としては、レーザトリマ、超音波方ツタ等によ
る方法がある。また接続方法としては、焦点イオンビー
ムによる蒸着、レーザCVD法を用いた方法等があげら
れる。切断方法に関しては比較的容易にできるが、接続
方法に関しては、装置が多がかりになり、また真空引き
とかガス導入といったプロセスを必要とするため基板処
理能力に問題となっていた。
As a cutting method, there are methods using a laser trimmer, an ultrasonic ivy, and the like. Examples of the connection method include vapor deposition using a focused ion beam and a method using a laser CVD method. Although the cutting method is relatively easy, the connecting method requires a large number of equipment and requires processes such as evacuation and gas introduction, which poses problems in substrate processing capacity.

:問題点を解決するための手段] 本発明は、前述の問題点を解決すべくなされたものであ
り、・あらかじめ補助配線を設けこれを用いて欠陥修復
を行えるようにした薄膜能動素子基板を提供することを
目的としたものであり、絶縁性基板上に行列状に電極を
配し、該行列状の電極交差点近傍に薄膜能動素子を設け
てなる薄膜能動素子基板において、絶縁膜をはさみ、上
下が導電性薄膜とからなる三層構、造の部分を有し、該
三層構造の部分の少なくとも一部がレーザ照射により上
下方向の導通がとられていることを特徴とする薄膜能動
素子基板である。
: Means for Solving the Problems] The present invention has been made to solve the above-mentioned problems, and includes: - A thin film active element substrate on which auxiliary wiring is provided in advance so that defects can be repaired using the auxiliary wiring. The present invention is intended to provide a thin film active element substrate in which electrodes are arranged in a matrix on an insulating substrate, and thin film active elements are provided near the intersections of the electrodes in the matrix, in which an insulating film is sandwiched, A thin film active element having a three-layer structure consisting of conductive thin films on the upper and lower sides, and at least a part of the three-layer structure being electrically connected in the vertical direction by laser irradiation. It is a board.

本発明は1分離した電極間には電気的に絶縁された補助
配線を形成しておくか、また意図的に電気的接触を取ら
ずにおく部分を作り、それらの部分でレーザにより上下
方向の導通を取ることによって、電気的に接続すること
を特徴としている。
In the present invention, an electrically insulated auxiliary wiring is formed between electrodes that are separated by one, or a portion is intentionally left without electrical contact, and a laser beam is applied to these portions in the vertical direction. It is characterized by electrical connection by establishing continuity.

ここで本方式による接続法の簡単な説明を加える。3層
構造部分の断面図を第4図(a)に示す、 (41)は
ガラス基板、(42)、 (44)は導電性薄膜を、(
43)は絶縁性g膜を示す、この構造の基板に対し上方
からレーザを照射すると、(b)に示すような形状にな
る。この時上部もしくは、下部の導電性材料が絶縁膜露
出面を覆い、上下の導電性薄膜の導通が取れるようにな
る。このような状態の物は洗浄工程、通電試験等にも何
ら変化を示さなかった。またこの補助配線は、行列状に
配した電極のうちいずれか一方の電極と同時に形成でき
るので、工程的には増やさずに修復機能を付加している
ばかりでなく、あらかじめ接続しやすいようにパターン
形状を工夫して種々の欠陥に対応できるように補助配線
を配しておくことで、この方法をより容易で確実なもの
にすることができるといった特徴を有する0例えば行列
状電極の重なり部分で発生した短絡を修復するために、
補助電極を形成しておき、欠陥が発生した場合には、欠
陥部を電気的     。
A brief explanation of the connection method using this method will be added here. A cross-sectional view of the three-layer structure is shown in Figure 4(a), where (41) is a glass substrate, (42) and (44) are conductive thin films, and (
43) shows an insulating g film. When a substrate with this structure is irradiated with a laser from above, it becomes shaped as shown in (b). At this time, the upper or lower conductive material covers the exposed surface of the insulating film, allowing electrical continuity between the upper and lower conductive thin films. Items in such a state did not show any change during the cleaning process, current test, etc. In addition, this auxiliary wiring can be formed at the same time as one of the electrodes arranged in a matrix, so not only does it add a repair function without increasing the number of steps, but it can also be patterned in advance to make it easier to connect. By devising the shape and arranging auxiliary wiring to deal with various defects, this method can be made easier and more reliable.For example, in the overlapped part of matrix electrodes, To repair the short circuit that has occurred,
An auxiliary electrode is formed in advance, and if a defect occurs, the defective part is electrically isolated.

に切断し補助電極を介して接続することにより表示欠陥
をなくすことを可能にすることもできる。
It is also possible to eliminate display defects by cutting the electrode and connecting it via an auxiliary electrode.

また本方式は、従来の修復方法と比較して、切断に用い
るレーザトリマをそのまま転用することができ、1台の
装置で切断、接続の両方の機能を持たせることができる
。さらに真空引き、ガス導入等は必要としないので基板
処理能力も大幅に向上させることができる。
In addition, in this method, compared to conventional repair methods, the laser trimmer used for cutting can be used as is, and a single device can have both cutting and connecting functions. Furthermore, since evacuation, gas introduction, etc. are not required, the substrate processing capacity can be greatly improved.

またさらに、種々の能動素子基板を作成した結果、欠陥
の発生場所は任意であり、近接した能動素子が欠陥とな
る確率は極めて低いので、1つの画素に複数の能動素子
を設けることにより第1の能動素子に欠陥がある場合に
は欠陥部分を削除して第2の能動素子を用いる事ができ
るように接続し、線欠陥1点欠陥をなくして薄膜能動素
子基板の歩留りを向上する事を可能にする。
Furthermore, as a result of creating various active element substrates, defects can occur at any location, and the probability of adjacent active elements becoming defective is extremely low. If there is a defect in the active element, the defective part is deleted and the second active element is connected so that a second active element can be used, thereby eliminating line defects and single point defects and improving the yield of thin film active element substrates. enable.

本発明は薄膜トランジスタ、薄膜ダイオード、等の能動
素子にも適応が可能であるが、以下の説明はTPTを例
にとって説明する。
Although the present invention can be applied to active elements such as thin film transistors and thin film diodes, the following description will be made using TPT as an example.

以下図面を参照しつつ説明する。This will be explained below with reference to the drawings.

第1図は本発明のTPTの代表的構造を示す平面図であ
る。全体はコープレナ構造のト2.ンジスタ2個と補助
電極を有する構造となっている。 (1)はアモルファ
スシリコン、多結晶シリコン、微結晶シリコン等からな
る半導体層を、(2)はAI等の金属からなるソースラ
インを、(3)は各画素のトランジスタのソース電極を
FIG. 1 is a plan view showing a typical structure of the TPT of the present invention. The whole structure has a coplanar structure. The structure has two resistors and an auxiliary electrode. (1) is a semiconductor layer made of amorphous silicon, polycrystalline silicon, microcrystalline silicon, etc., (2) is a source line made of metal such as AI, and (3) is a source electrode of a transistor of each pixel.

(0は第2のトランジスタのソース電極を示す、 (5
)、 (8)はそれぞれ第1及び第2のトランジスタの
ドレイン電極を示す、(7)はソース、ドレイン電極と
同様にAI等の金属からなるゲートラインを示す、(8
)はゲートラインとソースラインを絶縁するための絶縁
膜にあけられたコンタクトホールで、 (10)の表示
画素電極とドレイン電極(5)とを接続するためのもの
である。
(0 indicates the source electrode of the second transistor, (5
), (8) indicate the drain electrodes of the first and second transistors, respectively, (7) indicates the gate line made of metal such as AI like the source and drain electrodes, (8)
) is a contact hole made in an insulating film for insulating the gate line and source line, and is for connecting the display pixel electrode (10) and the drain electrode (5).

(8A)及び(3B)は本発明になる補助配線であり。(8A) and (3B) are auxiliary wiring according to the present invention.

ゲート電極と同様にAI等の金属からなり、ゲート電極
と同時に形成されればよい、また(11)はAI等の金
属からなる補助配線でソース電極と同時に形成されれば
よい0本発明では、この導電性薄膜による補助配線は、
AI、 Cr等の金属電極、140..79n02等の
透明電極等のいずれでもよく、蒸i、スパッタ等周知の
方法で形成されればよいが、この例のようにゲートライ
ンまたはソースラインの形成と同時に形成することによ
り、製造プロセスの追加の必要がないという利点を有し
ている。もっとも同様に、表示画素電極の形成と同時に
補助配線を形成してもよい。
Similarly to the gate electrode, it is made of a metal such as AI and may be formed at the same time as the gate electrode.Also, (11) is an auxiliary wiring made of a metal such as AI and may be formed at the same time as the source electrode. The auxiliary wiring using this conductive thin film is
Metal electrode such as AI, Cr, etc., 140. .. Any transparent electrode such as 79n02 may be used and may be formed by a well-known method such as evaporation or sputtering, but by forming it simultaneously with the formation of the gate line or source line as in this example, it is possible to add an additional manufacturing process. It has the advantage that there is no need for However, similarly, the auxiliary wiring may be formed simultaneously with the formation of the display pixel electrode.

本発明では、ゲートラインとソースラインの交差する重
なり部分(12)での短絡の修復のためにソースライン
の形成と同時にゲートラインを横切る位置に補助配線(
11)を形成し、ゲートラインの形成と同時にソースラ
インと補助配線(11)上にその両端が位置するように
補助配線(9B)を重なり部分1個に対し2個形成して
おり、このような構成をとることにより、補助配線(8
B)とソースライン(2)、補助配線(IB)と補助配
線(11)は絶縁されており、万一補助配線(11)と
ゲートライン(7)が短絡を生じていても補助配線(1
1)とソースライン(2)を導通させない限す、ソース
ラインには何ら影響を与えなく不良を増加させない。
In the present invention, an auxiliary wiring (
11), and at the same time as the gate line is formed, two auxiliary wirings (9B) are formed for each overlapping part so that both ends are located on the source line and the auxiliary wiring (11). By adopting this configuration, the auxiliary wiring (8
B) and the source line (2), and the auxiliary wiring (IB) and the auxiliary wiring (11) are insulated, so even if there is a short circuit between the auxiliary wiring (11) and the gate line (7), the auxiliary wiring (1
As long as the source line (1) and the source line (2) are not electrically connected, the source line will not be affected and the number of defects will not increase.

又、第2のトランジスタのソース電極(4)とソースラ
イン(2)上にゲートラインの形成と同時に補助配線(
8A)を形成しており、これも補助配線(8A)とソー
スライン(2)、ソース電極(4)の両方とも短絡を生
じるかレーザで導通をとらない限り、第2のトランジス
タはソースラインに接続されないため、不良を生じるこ
とはない。
Also, at the same time as forming the gate line on the source electrode (4) and source line (2) of the second transistor, the auxiliary wiring (
8A), and unless both the auxiliary wiring (8A), the source line (2), and the source electrode (4) are short-circuited or made conductive by laser, the second transistor will not connect to the source line. Since it is not connected, no defects will occur.

第2のトランジスタのドレイン電極は補助配線を用いな
いで表示画素電極(lO)と重ねられているが、これも
ドレイン電極を2分し、一方はドレイン電極、他方は表
示画素電極とコンタクトホールで接続した電極とし、こ
の両方の電極と重なるように補助配線を設けたり、逆に
表示画素電極を2分し、ドレイン電極とコンタクトホー
ルで接続した電極と表示画素電極の両方の     ;
電極なるように補助配線を設けてもよい。
The drain electrode of the second transistor is overlapped with the display pixel electrode (lO) without using auxiliary wiring, but this also divides the drain electrode into two, with one being the drain electrode and the other being the display pixel electrode and the contact hole. You can connect the electrodes and provide auxiliary wiring to overlap both electrodes, or conversely, divide the display pixel electrode into two and connect both the electrode and the display pixel electrode with the drain electrode through a contact hole;
Auxiliary wiring may be provided to serve as an electrode.

この例においては、第1のトランジスタにおいて、ゲー
ト・ドレイン短絡、ゲート・ソース短絡、特性の不良等
がおとうた場合には、AもしくはBの部分または両方の
部分において、このトランジスタをレーザトリマ等によ
り切断し、その後ソースライン(2)と第2のトランジ
スタのソース電極(0とを補助配線(8A)との重なり
部分で上下方向に導通させることにより補助配線(θA
)を介して接続し、ざらにCの透明導電膜(1G)/絶
縁膜/金属(8)の3層構造の部分でレーザにより上下
方向に導通な取ることによって接続し、この第2のトラ
ンジスタを用いて、動作させるようにすることができる
。修復後の状態を第5図に示す、A、Hの部分で電極が
切断され、(13)にはレーザによる上下導通時の穴が
開いている。Cの部分でも同様に穴が開いている。この
部分では、コンタクトを確実にするために複数回、レー
ザを照射している状態を示す、またゲートライン(7)
とソースライン(2)との亜なり部分(12)において
ゲート・ソース短絡が発生したような場合には、Dの部
分でソースラインを切断し、補助配線(8B)及び補助
品!1t(11)の重なり部分(14)及びソースライ
ン(2)と補助配線(9B)の重なり部分(15)にお
いて、レーザにより上下方向導通を取ることで欠陥を回
避し表示欠陥をなくすことが可能になる。
In this example, if a gate-drain short circuit, gate-source short circuit, defective characteristics, etc. occur in the first transistor, this transistor is cut off at the A or B portion or both portions using a laser trimmer or the like. Then, the auxiliary wiring (θA
), and the second transistor You can make it work using . The state after repair is shown in FIG. 5. The electrodes are cut at parts A and H, and holes are made at (13) for vertical conduction by laser. There is a hole in the C part as well. This part shows that the laser is irradiated multiple times to ensure contact, and the gate line (7)
If a gate-source short circuit occurs at the subjunction (12) between the source line (2) and the source line (2), cut the source line at the part D and remove the auxiliary wiring (8B) and the auxiliary parts! At the overlapping part (14) of 1t (11) and the overlapping part (15) between the source line (2) and the auxiliary wiring (9B), it is possible to avoid defects and eliminate display defects by creating vertical conduction using a laser. become.

以上の説明は、コープレナfiTFTの場合について説
明したが、スタガー型、逆スタガー型、ダブルゲート型
やEurodisplay ’84 Proc−eed
jngs p、252に示されているような簡素化プe
f−1=スのTPTにも応用でき、特にTPTの構造に
制限されるものではない。
The above explanation deals with the case of coplanar fiTFT, but it also applies to stagger type, reverse stagger type, double gate type and Eurodisplay '84 Proc-eed
jngs p, 252
It can also be applied to a TPT with f-1=s, and is not particularly limited to the structure of the TPT.

さらにこの他遮光膜、液晶配向膜、カラーフィルタ、偏
光板等を形成したり、トランジスタをi1i素あたり2
個以上形成したりしてもよく、種々の応用が可能である
In addition, we also form light shielding films, liquid crystal alignment films, color filters, polarizing plates, etc., and
It is also possible to form more than one, and various applications are possible.

[作用] 本発明のTPTによれば、第3図のような例と比較して
、プロセス的には、まったく変えることなく、電極間相
互の短絡による欠陥を容易に修復し、無欠陥表示を行う
ことが可能になる、この方法によれば製造歩留りを容易
に 1.00%に近づけられるので、TPTマトリクス
パネルを情報表示装置として用いる際に、従来から用い
られているドツトマトリクス等と比べた時の製造コスト
が高いといった欠点を充分補うことができる。
[Operation] According to the TPT of the present invention, compared to the example shown in FIG. 3, defects caused by short circuits between electrodes can be easily repaired without changing the process at all, and a defect-free display can be achieved. With this method, the manufacturing yield can be easily brought close to 1.00%, so when using the TPT matrix panel as an information display device, it is much easier to use than the conventionally used dot matrix, etc. This can fully compensate for the disadvantages of high manufacturing costs.

「実施例」 以下に本発明による補助配線を用いたTPTの実施例を
示す、TPTの構造は前出の第1図に示したものと同一
である。ガラス基板上にプラズマCVD法により200
0人の非晶質酸化シリコンをシランガスと笑気ガスの混
合ガスにより形成した。その後、アモルファスシリコン
層を 100%シランガスを用いて2000人形成した
``Example'' An example of a TPT using auxiliary wiring according to the present invention will be shown below.The structure of the TPT is the same as that shown in FIG. 1 above. 200 mm by plasma CVD method on a glass substrate.
Amorphous silicon oxide was formed using a mixed gas of silane gas and laughing gas. Thereafter, 2,000 amorphous silicon layers were formed using 100% silane gas.

このアモルファスシリコン層をフォトリソグラフィーの
工程により図に示すような形状にパターニングした後に
AIを3000人EB蒸着法により蒸着した。この後、
パターニングによりソースライン(2)、ソース電極(
3)、 (4)、  ドレイン電極(5)、 (8)及
び補助配線(11)を形成した。この上に絶縁膜として
非晶質酸化シリコン層2000人をプラズマCVD法に
より、またAI層5000人をEB蒸着法によって蒸着
した。この後、まずパターニングにより、ゲートライン
(7)及び補助配線(9A)、 (9B)を形成したの
ちに、ドライエツチング法によりコンタクトホール(8
)をあけた、この後ITO膜をEB蒸着法により形成し
、リフトオフを用いて表示画素電極(1o)をパターニ
ングした。
This amorphous silicon layer was patterned into the shape shown in the figure by a photolithography process, and then AI was deposited by a 3000-person EB deposition method. After this,
By patterning, source line (2), source electrode (
3), (4), Drain electrodes (5), (8) and auxiliary wiring (11) were formed. Thereon, as an insulating film, an amorphous silicon oxide layer of 2,000 layers was deposited by plasma CVD, and an AI layer of 5,000 layers was deposited by EB evaporation. After this, first, a gate line (7) and auxiliary wirings (9A) and (9B) are formed by patterning, and then a contact hole (8) is formed by dry etching.
) was opened, then an ITO film was formed by EB evaporation, and a display pixel electrode (1o) was patterned using lift-off.

上記のような手法を用いて、 800μ層ピッチ、50
本×50本のマドリスクパネルを10枚製作し、第3図
のようなTPT基板と比較した。
Using the method described above, 800μ layer pitch, 50
Ten Madrisk panels with 50 books were produced and compared with a TPT board as shown in Figure 3.

本発明の補助配線等を形成したことによる開口率の減少
は、数%程度であり、表示品位の点ではまったく問題は
なかった。また従来のTPTと比較しても補助配線の形
成に伴う欠陥の増加、トランジスタ特性の劣化等はまっ
たく見られなかった。この基板について短絡検査を行っ
た結果は従来と同レベルの0〜3個/枚であった。
The decrease in aperture ratio due to the formation of the auxiliary wiring and the like of the present invention was on the order of several percent, and there was no problem at all in terms of display quality. Furthermore, when compared with conventional TPT, no increase in defects or deterioration of transistor characteristics due to the formation of auxiliary wiring was observed. A short circuit test was performed on this board, and the result was 0 to 3 short circuits per board, which is the same level as the conventional one.

短絡の種類は、ケート・ソース間短絡が2ケ所、ゲート
・ドレイン間短絡が1ケ所であった。ゲート・ドレイン
間短絡の発生場所においては、短絡点のソース電極の根
本Aとドレイン電極Bとをレーザで切断後、補助配線(
9A)とソースライン(2)及びソース電極(4)との
重なり部分及び第2のトランジスタのドレイン電極(6
)と表示画素電極(10)との重なり部分Cに5JL1
1角のレーザを照射し上下の導通を取り、第2のトラン
ジスタを用いる事ができるように接続して修復を行った
The types of short circuits were two gate-source short circuits and one gate-drain short circuit. At the location where the gate-drain short circuit occurs, after cutting the root A of the source electrode and the drain electrode B at the point of the short circuit with a laser, cut the auxiliary wiring (
9A) with the source line (2) and source electrode (4) and the drain electrode (6) of the second transistor.
) and the display pixel electrode (10) overlap part C with 5JL1.
Repair was carried out by irradiating a single corner laser to establish continuity between the upper and lower sides, and connect it so that a second transistor could be used.

ゲート・ソース間短絡の発生場所においては、短絡点の
ソースラインのゲートラインとの交差点の両側りをレー
ザで切断後、補助配線(9B)とソースライン(2)と
の重なり部分(15)及び補助配!! (9B)と補助
配線(11)との重なり部分(14)に5ル■角のレー
ザを照射して上下の導通を取り、ゲート・ソース間短絡
点をう回してソースラインを接続して修復を行った。こ
れにより欠陥がなくなった基板をセル化し−C表示品位
を確認したが、修復部分での表示は他の部分と比べ、何
ら遜色のないものであり、通電による信頼性試験でも特
性の劣化も修復しなかった部位と差はなかった。
At the location where the gate-source short circuit occurs, after cutting both sides of the intersection of the source line and the gate line at the short-circuit point with a laser, cut the overlapping part (15) of the auxiliary wiring (9B) and the source line (2) Auxiliary arrangement! ! Irradiate the overlapped part (14) between (9B) and the auxiliary wiring (11) with a 5 square square laser to establish vertical continuity, bypass the gate-source short-circuit point, and connect the source line to repair it. I did it. As a result, the defect-free board was made into cells and the -C display quality was confirmed, and the display in the repaired area was no inferior to other areas, and the deterioration of characteristics was also repaired in reliability tests due to energization. There was no difference between the areas that were not treated.

[発明の効果] 以上のように本発明は補助電極を設けることのみで、T
FT等薄膜詣動素子を用いた表示欠陥を完全に、かつ容
易に修復できるようになる。これにより製品の不良品率
を著しく低減することができ、従来から用いられている
ドツトマトリクスタイプと比べ、アクティブマトリクス
タイプの問題点であった製造歩留りを上げ、製造コスト
を低く押えることができる0本発明はアクティブマドリ
スクパネルの実用化に大きく貢献できるものである。
[Effects of the invention] As described above, the present invention can reduce T by simply providing an auxiliary electrode.
Display defects using thin film moving elements such as FT can be completely and easily repaired. This can significantly reduce the defect rate of products, and compared to the dot matrix type that has been used in the past, it is possible to increase the manufacturing yield and keep manufacturing costs low, which was a problem with the active matrix type. The present invention can greatly contribute to the practical application of active Madrisk panels.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明のTPTの代表例の導通をとる前の状態
を示す平面図。 第2図はアクティブマトリクスパネルの代表例の概念図
。 第3図は、従来のTPTの例を示す平面図。 第4図(a)、 (b)は水力式により上下方向の導通
を取る前の状態(a)と取った後の状態(b)を示す断
面図。 第5図は修復後のTPTの接続状態を示す平面図。 に半導体層 2:ソースライン 3.4二 ソース電極 5.6:  ドレイン電極 7:ゲートライン 8ニコンタクトホール 9A、98.11 :  補助配線 lO:  表示画素電極 第 1 の 第2図 第40 (Q)             (b)第3 図
FIG. 1 is a plan view showing a typical example of the TPT of the present invention in a state before conduction is established. FIG. 2 is a conceptual diagram of a typical example of an active matrix panel. FIG. 3 is a plan view showing an example of a conventional TPT. FIGS. 4(a) and 4(b) are cross-sectional views showing a state (a) before vertical continuity is established by a hydraulic system and a state (b) after it is established. FIG. 5 is a plan view showing the connection state of the TPT after repair. Semiconductor layer 2: Source line 3.42 Source electrode 5.6: Drain electrode 7: Gate line 8 Contact hole 9A, 98.11: Auxiliary wiring lO: Display pixel electrode ) (b) Figure 3

Claims (7)

【特許請求の範囲】[Claims] (1)絶縁性基板上に行列状に電極を配し、該行列状の
電極交差点近傍に薄膜能動素子を設けてなる薄膜能動素
子基板において、絶縁膜をはさみ、上下が導電性薄膜と
からなる三層構造の部分を有し、該三層構造の部分の少
なくとも一部がレーザ照射により上下方向の導通がとら
れていることを特徴とする薄膜能動素子基板。
(1) A thin film active element substrate in which electrodes are arranged in a matrix on an insulating substrate, and thin film active elements are provided near the intersections of the electrodes in the matrix, with an insulating film sandwiched between them, and conductive thin films on the upper and lower sides. 1. A thin film active element substrate having a three-layer structure, and at least a part of the three-layer structure being electrically connected in the vertical direction by laser irradiation.
(2)三層構造の部分の少なくとも一方の導電性薄膜が
、他の導電性薄膜から絶縁された補助配線である特許請
求の範囲第1項記載の薄膜能動素子基板。
(2) The thin film active element substrate according to claim 1, wherein at least one conductive thin film of the three-layer structure portion is an auxiliary wiring insulated from other conductive thin films.
(3)行列状の電極の電極交差点近傍に、一方の電極で
ある第1の電極にほぼ平行にかつ他方の電極である第2
の電極を横切るように補助配線を設けてなる特許請求の
範囲第2項記載の薄膜能動素子基板。
(3) Near the electrode intersection of the matrix-shaped electrodes, a second electrode is placed approximately parallel to one electrode, the first electrode, and the other electrode is the second electrode.
3. The thin film active element substrate according to claim 2, wherein auxiliary wiring is provided to cross the electrode.
(4)補助配線の一端とその一端でかつ第1の電極とそ
の他端で絶縁膜をはさんで三層構造を形成した第2の補
助配線を設けてなる特許請求の範囲第3項記載の薄膜能
動素子基板。
(4) A second auxiliary wiring having a three-layer structure formed by sandwiching an insulating film between one end of the auxiliary wiring and the first electrode and the other end of the auxiliary wiring. Thin film active device substrate.
(5)補助配線が、第1の電極と同時に形成される特許
請求の範囲第3項記載の薄膜能動素子基板。
(5) The thin film active element substrate according to claim 3, wherein the auxiliary wiring is formed simultaneously with the first electrode.
(6)補助配線が、第1の電極と同時に形成され、第2
の補助配線が第2の電極と同時に形成される特許請求の
範囲第4項記載の薄膜能動素子基板。
(6) The auxiliary wiring is formed simultaneously with the first electrode, and the second
5. The thin film active element substrate according to claim 4, wherein the auxiliary wiring is formed simultaneously with the second electrode.
(7)補助配線とその両端で夫々絶縁膜をはさんで三層
構造とされた2個の第2の補助配線により、第1の電極
のバイパスを形成しうるようにした特許請求の範囲第4
項記載の薄膜能動素子基板。
(7) A bypass of the first electrode can be formed by an auxiliary wiring and two second auxiliary wirings having a three-layer structure with an insulating film sandwiched between each end of the auxiliary wiring. 4
The thin film active element substrate described in .
JP60161248A 1985-07-23 1985-07-23 Thin film active element substrate Expired - Lifetime JP2655638B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60161248A JP2655638B2 (en) 1985-07-23 1985-07-23 Thin film active element substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60161248A JP2655638B2 (en) 1985-07-23 1985-07-23 Thin film active element substrate

Publications (2)

Publication Number Publication Date
JPS6222455A true JPS6222455A (en) 1987-01-30
JP2655638B2 JP2655638B2 (en) 1997-09-24

Family

ID=15731468

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60161248A Expired - Lifetime JP2655638B2 (en) 1985-07-23 1985-07-23 Thin film active element substrate

Country Status (1)

Country Link
JP (1) JP2655638B2 (en)

Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01125951A (en) * 1987-11-11 1989-05-18 Hitachi Ltd Transistor circuit device
EP0365244A2 (en) * 1988-10-17 1990-04-25 Sharp Kabushiki Kaisha An active matrix substrate
EP0372898A2 (en) * 1988-12-06 1990-06-13 Sharp Kabushiki Kaisha Active matrix display apparatus
JPH02157828A (en) * 1988-12-12 1990-06-18 Hosiden Electron Co Ltd Liquid crystal display element
JPH02193114A (en) * 1989-01-23 1990-07-30 Sharp Corp Manufacture of display device
EP0380265A2 (en) * 1989-01-23 1990-08-01 Sharp Kabushiki Kaisha A method of manufacturing active matrix display apparatuses
EP0381428A2 (en) * 1989-01-31 1990-08-08 Sharp Kabushiki Kaisha Active matrix substrate and active matrix display display apparatus
EP0390505A2 (en) * 1989-03-28 1990-10-03 Sharp Kabushiki Kaisha Matrix display apparatus
JPH02294624A (en) * 1989-05-10 1990-12-05 Sharp Corp Manufacture of active matrix display device
JPH0317614A (en) * 1989-06-15 1991-01-25 Sharp Corp Production of active matrix display device
JPH03113421A (en) * 1989-09-27 1991-05-14 Sharp Corp Active matrix display device
EP0430418A2 (en) * 1989-11-30 1991-06-05 Kabushiki Kaisha Toshiba Liquid crystal display and method of manufacturing the same
EP0482737A2 (en) * 1990-09-27 1992-04-29 Sharp Kabushiki Kaisha Active matrix display device
US5392143A (en) * 1989-11-30 1995-02-21 Kabushiki Kaisha Toshiba Liquid crystal display having drain and pixel electrodes linkable to a wiring line having a potential
US5469025A (en) * 1990-09-27 1995-11-21 Sharp Kabushiki Kaisha Fault tolerant active matrix display device
KR20020091697A (en) * 2001-05-31 2002-12-06 주식회사 현대 디스플레이 테크놀로지 Liquid crystal display
KR100430800B1 (en) * 1996-12-31 2004-09-04 삼성전자주식회사 Ips switching mode lcd for simple repair of opened data lines
US7209193B2 (en) 1993-03-04 2007-04-24 Samsung Electronics Co., Ltd. Matrix-type display device capable of being repaired in pixel unit

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59101693A (en) * 1982-12-02 1984-06-12 セイコーエプソン株式会社 Active matrix substrate

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59101693A (en) * 1982-12-02 1984-06-12 セイコーエプソン株式会社 Active matrix substrate

Cited By (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01125951A (en) * 1987-11-11 1989-05-18 Hitachi Ltd Transistor circuit device
EP0365244A2 (en) * 1988-10-17 1990-04-25 Sharp Kabushiki Kaisha An active matrix substrate
US5076666A (en) * 1988-12-06 1991-12-31 Sharp Kabushiki Kaisha Active matrix display apparatus with drain electrode extensions
EP0372898A2 (en) * 1988-12-06 1990-06-13 Sharp Kabushiki Kaisha Active matrix display apparatus
JPH02157828A (en) * 1988-12-12 1990-06-18 Hosiden Electron Co Ltd Liquid crystal display element
EP0373586A2 (en) * 1988-12-12 1990-06-20 Hosiden Corporation Liquid crystal display device
JPH02193114A (en) * 1989-01-23 1990-07-30 Sharp Corp Manufacture of display device
EP0380265A2 (en) * 1989-01-23 1990-08-01 Sharp Kabushiki Kaisha A method of manufacturing active matrix display apparatuses
EP0381428A2 (en) * 1989-01-31 1990-08-08 Sharp Kabushiki Kaisha Active matrix substrate and active matrix display display apparatus
EP0390505A2 (en) * 1989-03-28 1990-10-03 Sharp Kabushiki Kaisha Matrix display apparatus
JPH02294624A (en) * 1989-05-10 1990-12-05 Sharp Corp Manufacture of active matrix display device
JPH0317614A (en) * 1989-06-15 1991-01-25 Sharp Corp Production of active matrix display device
JPH03113421A (en) * 1989-09-27 1991-05-14 Sharp Corp Active matrix display device
EP0430418A2 (en) * 1989-11-30 1991-06-05 Kabushiki Kaisha Toshiba Liquid crystal display and method of manufacturing the same
US5392143A (en) * 1989-11-30 1995-02-21 Kabushiki Kaisha Toshiba Liquid crystal display having drain and pixel electrodes linkable to a wiring line having a potential
EP0482737A2 (en) * 1990-09-27 1992-04-29 Sharp Kabushiki Kaisha Active matrix display device
US5469025A (en) * 1990-09-27 1995-11-21 Sharp Kabushiki Kaisha Fault tolerant active matrix display device
US5508591A (en) * 1990-09-27 1996-04-16 Sharp Kabushiki Kaisha Active matrix display device
US7209193B2 (en) 1993-03-04 2007-04-24 Samsung Electronics Co., Ltd. Matrix-type display device capable of being repaired in pixel unit
KR100430800B1 (en) * 1996-12-31 2004-09-04 삼성전자주식회사 Ips switching mode lcd for simple repair of opened data lines
KR20020091697A (en) * 2001-05-31 2002-12-06 주식회사 현대 디스플레이 테크놀로지 Liquid crystal display

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