JPS62219137A - Processing system for logical simulator - Google Patents

Abstract

PURPOSE:To attain highly speedy simulation by forming the logical model of a new circuit to be simulated from the description of the supervising conditions to the special gate of the circuit to be simulated, and executing supervising processing in a hardware mode. CONSTITUTION:A special gate supervising part 3-1 confirms that event data are the output of the special gate circuit, sends a supervising conditions establishing signal to a control part 3-2 and the control part 3-2 outputs the supervising conditions establishing interrupting signal to show that the supervising conditions are established, to a simulation control computer 2. The simulation control computer 2 to receive an interrupting signal executes 'interrupting processing group' in a DO block at the time of establishing an iF sentence and returns an executing right to a simulation processing device 3 again. When the memory area of an event recording memory 3-5-1 is filled with the event data, the control part 3-2 transfers the event data to DASD7. Consequently, the supervising conditions described in the program are inspected in a hardware mode by a model, and the high speed of the processing speed can be executed.

Description

[Detailed Description of the Invention] [Summary] The present invention is a processing method of a logic simulation device when simulating a circuit to be simulated, comprising:
A new logical model of the circuit to be simulated is created from the monitoring condition description for a specific gate of the circuit to be simulated, and monitoring processing is performed using hardware to enable high-speed simulation.

[Industrial application field]

The present invention relates to a processing method for a logic simulation device that verifies the correctness of a circuit by comparing the operation of the circuit with an expected value.

In recent years, circuits and devices have become more complex, and their operations have become more diverse. A logic simulation device is used as a means to confirm the correctness of the operations of these circuits and devices. On the other hand, circuits to be simulated are becoming more complex and require more time to verify.

Therefore, there is a need for a processing method for a logic simulation device that can perform simulation processing at high speed.

[Conventional technology]

As shown in FIG. 3, the conventional logic simulation device 1o includes a simulation control computer 20 that controls the simulation and verifies the simulation results, and a simulation control computer 20 that performs calculations on a model of the circuit to be simulated using a simulation control program. The simulation processing device 30 sends calculation results to the simulation control computer 20.

That is, the simulation control computer 2o performs simulation verification using a program, and the simulation processing device 3o performs arithmetic processing of the model using hardware. The validity of this model must be constantly monitored, and therefore the speed of a high-speed simulation processing device cannot be utilized.

[Problem that the invention seeks to solve]

In the processing method of the conventional logic simulation apparatus described above, the simulated circuit processed by hardware can be processed at high speed, but the validity check of the circuit is processed by the simulation control computer by software. Therefore, in order to perform simulation processing at high speed, it is necessary to perform a validity check using hardware to reduce the need for software intervention.

SUMMARY OF THE INVENTION In view of the above-mentioned conventional situation, it is an object of the present invention to provide a processing method for a logic simulation device that can reduce the number of verifications and perform simulation processing at high speed.

[Means for solving problems]

In order to address the above problem, the present invention is configured such that a simulation control computer that verifies simulation results creates a new logic model of a simulated circuit from a monitoring condition description for a specific gate of the simulated circuit. .

[Effect]

Monitoring condition description is based on simulation system f311:17
Since the logic model is converted into a new logical model of the circuit to be simulated by the processor, the validity check that was previously checked by software is now processed by hardware in conjunction with the circuit to be simulated, thereby improving speed.

〔Example〕

FIG. 1 is a block diagram of a simulation device to which the present invention is applied, and the simulation control computer 2
is the port ^SD6 that stores the input event (hereinafter referred to as large scale event) and the AS 1) that stores the simulation result.
117.

The simulation control computer 2 has, for example, 100
00: "Instruct the simulation processing device 3 to perform two simulations.

When the computation of the simulation simulator 3 is completed, the calculation is normally returned to the simulation control computer 2 to perform the next simulation. Furthermore, if the monitoring condition is satisfied at the 100th clock, the specific gate monitoring section 3-1 interrupts the simulation control computer at that point.

Prior to the 3Q, the process by which the simulation control computer 2 creates a new circuit to be simulated will be explained with reference to FIG. In principle, the simulated circuit 5 includes, for example, AND circuits 5-1 to 5-3, an OR circuit 5-4, and a gate circuit 5, as shown in FIG. 2(a).
-5. However, the monitoring conditions of the gate circuit 5-5 are described as shown in FIG.
This verification was handled by software. The gate circuit 5-5 to which the above-mentioned monitoring condition is attached is a specific gate circuit.

The simulation control computer 2 according to the present invention includes:
A new simulated circuit 4 is created from the circuits shown in FIGS. 2(al) and (b). That is, as shown in FIG. 2(C), the exclusive OR circuit 4-1 is
Create a circuit added to.

The example in Fig. 2 fb) is the simplest example, but a more complicated expression can be written in the iF (gate circuit 5-5-'1'') section shown here. For example, iF (conditional expression A
1 conditional expression 1 conditional expression C) Expression A is obtained.

A logical OR of the formula C of 2B1 is created, and the final result output becomes a monitored gate similar to the exclusive OR circuit 4-1.

The configuration of the simulation processing device 3 will be described below. The simulation processing device 3 includes a control unit 3-2 that manages control, a specific gate monitoring unit 3-1 having a monitoring gate registration memory 3-1-1 in which the above-described monitoring gate 4-1 is registered. An event input processing unit 3-3 having an input event memory 3-3-1 that stores input events input by the control unit 3-2 from the DASD 6 during device operation.
, a gate arithmetic processing section 3-4 having a model storage memory 3-4-1 for storing the above-mentioned new logic model of the circuit to be simulated, and an event for recording event data output from the gate arithmetic processing section 3-4. It is composed of an event output processing section 3-5 having a recording memory 3-5-1. Note that the event data is formed from the gate circuit name and its output value.

The operation will be explained below. The new simulation circuit model created by the simulation control computer 2 is stored in the model storage memory 3-4-1 by the control unit 3-2. On the other hand, input events of the DASD 6 are stored in the input event memory 3-3-1. The event input processing section 3-3 sends the input event from the input event memory 3-3-1 to the gate calculation processing section 3-4.

The gate calculation processing unit 3-4 has a model storage memory 3-4-
1 and records the event data in the event recording memory 3-5-1.

Further, the event data is sent to the specific gate monitoring section 3-1. The specific gate monitoring unit 3-1 compares the contents of the monitoring gate registration memory 3-1-1 and registers this event.
After confirming that the data is the output of a specific gate circuit, a monitoring condition fulfillment signal is sent to the control unit 3-2.

The control unit 3-2 includes a simulation control computer 2
An interrupt signal indicating that the monitoring condition has been satisfied is outputted.

Upon receiving the interrupt signal, the simulation control computer 2 executes the "interrupt processing group" in the DO block when the iF statement in bl is established as shown in FIG.
Return execution rights to . In addition, event recording memory 3-5-1
When the storage area of the controller 3 is filled with event data, the controller 3
-2 transfers event data to DASD7.

Therefore, the monitoring conditions described in the program are verified by hardware using the model, and the processing speed can be increased.

[Effects] As is clear from the above description, according to the present invention, comparison checks, abnormality detection checks, etc., which were conventionally performed on a simulation control computer, are described in conditional expressions, and these conditional expressions can be applied to the circuit. The simulation is performed at the same time as the original circuit to be simulated, which is extremely effective in increasing the processing speed of the logic simulation device.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a simulation device to which the present invention is applied; Fig. 2 is an explanatory diagram for creating a new simulation circuit according to the present invention; Fig. 2 Ta) is a diagram of the original simulated circuit;
Figure (bl is the original monitoring condition description diagram, Figure 2 (C) is the new simulated circuit diagram, and Figure 3 is the configuration diagram of the conventional logic simulation device. In the figure, l and 10 are the logic simulation device ,2
and 20 are simulation control computers, 3 and 30
4 indicates a simulation processing device, and 4 indicates a new circuit to be simulated. 1 mN simulation device - Block diagram of the simulation device used if the present invention No. 12 (al city) Ship-regular simulation route (C) Current simulation cycle based on t≦a month 1st sip of the book, Figure 2

Claims (1)

[Claims] A processing method for a logic simulation device (1) comprising a simulation control computer (2) that controls simulation operations and verifies results, and a simulation processing device (3) that simulates a circuit to be simulated, wherein the simulation control The computer (2) creates a new simulated circuit (
4) A processing method of a logic simulation device, characterized in that a logic model is formed, and the simulation processing device (3) performs simulation using the logic model.