JPS62203362A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To make a high temperature process applicable by a method wherein one conductivity type diffused layer is formed on a groove part, sidewalls and bottom thereof formed on one conductivity type semiconductor substrate and then a diffused layer of the other conductivity type is provided through the intermediary of insulator layers. CONSTITUTION:A P-type diffused layer 10 is formed on the sidewalls and bottom of a groove part 12 formed on a low concentration P-type semiconductor substrate 20. An N-type diffusion layer 8 is formed on the diffused layer 10 through the intermediary of insulator layers 21. Besides, a signal charge storing electrode 4 connecting to the layer 8 is formed in the groove 12 through the intermediary of a thin dielectric layer 2. Furthermore, a reading and writing MOS transistor 13 with a word line 6 is formed between the layer 8 and a bit line 5. Through these procedures, a high temperature process can be made applicable to manufacture a semiconductor memory easily composed of a CMOS structure.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to semiconductor memory devices, particularly dynamic memories.

Conventional Technology Figure 2 shows the structure of a conventional trench capacitor type memory cell (IEDM).
'85, pp. 710)a The structure and operation of this memory cell will be explained using FIGS. 2 and 3. This memory cell includes a low concentration P type semiconductor layer 9. formed on a high concentration P type semiconductor substrate 1. Groove portion 12. Groove 12
A dielectric layer formed on the side surface of 2. A storage electrode 4 formed in the trench through the dielectric layer 2 and connected to the N-type diffusion layer 8. and a read/write MOS transistor section 13. During writing, a signal voltage is applied from the bit line 6 to the diffusion portion 7°MOS transistor portion 13.
．． Via the diffusion section 8.

The data is written into a storage capacitor formed between the storage electrode 4 and the highly doped P-type substrate 1, and stored as a signal charge. During reading, the signal charge stored in the storage capacitor formed between the storage electrode 4 and the heavily doped P-type substrate 1 is read out as a signal voltage to the bit line 6 through the reverse path.

Problems to be Solved by the Invention In such a conventional memory cell structure, since a low concentration P-type semiconductor layer is formed on a high concentration P-type semiconductor substrate,
The drawback is that it cannot be passed through high-temperature processes.

This is because the high-concentration P-type layer spreads into the upper low-concentration P-type layer by thermal diffusion due to the high-temperature process.

Furthermore, when trying to realize a 0MO3 structure.

First, as shown in FIG. 3(a), in order to form a well in the substrate 3o, a layer having an impurity distribution 32 as shown in FIG. 3(0)) is formed on the semiconductor substrate 30 by ion implantation 31. The high temperature heat treatment causes impurities to be diffused in the depth direction of the semiconductor substrate, resulting in an impurity distribution 33 as shown in FIG. 3(c). here.

High-temperature heat treatment is necessary because the region where the impurity density gradient is constant (the distribution area indicated by 34 in FIG. 3(C)) is for stable operation of the MOS transistor formed in the well, and for the MOS transistor formed in the well. This is because it is essential for reducing variations in transistor characteristics.

When trying to realize a 0MO3 structure like this, a high temperature process is unavoidable, so it is also difficult to realize it with the conventional structure.

The present invention has been made in view of the above points, and is based on the conventional CM
The purpose is to enable the application of a high temperature process similar to the OS process.

Means for Solving the Problems In order to solve the above problems, the present invention provides a groove formed on a P-type semiconductor substrate, a P diffusion layer formed on the side and bottom surfaces of the groove, and a P diffusion layer formed on the side and bottom surfaces of the groove. To electrically insulate the N type diffusion layer formed above the diffusion layer, the P diffusion layer, and the N type diffusion layer.

formed in the groove and connected to the N-type diffusion layer through an insulating layer formed between the P diffusion layer and the N-type diffusion layer, and a thin dielectric layer formed on the side surface of the groove. It has a structure consisting of a storage electrode for accumulating signal charges, and an N-type MOS transistor for reading formed between the N-type diffusion layer and the bi-node line.

Function: Due to the above-described structure, the present invention enables the use of a high-temperature process unlike the conventional example, thereby making it possible to realize a 0MO3 structure.

Embodiment FIG. 1 shows the structure of a semiconductor memory device in an embodiment of the present invention.

The memory cell in this embodiment has a trench 12. formed on a low concentration P-type semiconductor substrate 20. The P-type diffusion layer 10 formed on the side and bottom surfaces of the groove portion 12 and the N-type diffusion layer 8° formed above the P-type diffusion layer 10 electrically insulate the P-type diffusion layer 10 and the N-type diffusion layer 8 Therefore, an insulator layer 21. formed between the P-type diffusion layer 10 and the N-type diffusion layer 8. A storage electrode 4 for accumulating signal charges is formed in the groove 12 through a thin dielectric layer 2 formed on the bottom and side surfaces of the groove 12 and connected to the N-type diffusion layer 8. It is formed between the N-type diffusion layer 8 and the bit line 6, and is composed of a read/write MOS transistor section 13 having a word line 6. 22 and 23 are insulating films.

The difference from the conventional example is that an insulator layer 21 is formed to vertically separate the N-type diffusion layer 8 and the P-type diffusion layer 10, and a high-concentration P-type semiconductor substrate is not used, and a low-concentration P-type semiconductor substrate is used. The advantage is that the semiconductor substrate 2o can be used.

Next, the operation of this embodiment will be explained. During writing, the signal voltage is applied from the B,..., G lines 6 to the diffusion section 7°MOS).
Ransistor section 13. Via the diffusion section 8.

The data is written into a storage capacitor formed between the storage electrode 4 and the P-type diffusion layer 10, and stored as a signal charge. During reading, the signal charge stored in the storage capacitor formed between the storage electrode 4 and the P-type diffusion layer 10 is read out as a signal voltage to the bit line 6 through the reverse path.

Effects of the Invention As described above, according to the present invention, unlike the conventional example, there is no need to use a high concentration P-type semiconductor substrate.

As a result, there is the advantage that high temperature processes can be used. Furthermore, since high temperature processes can be used, CMOS structures are easier to implement than conventional structures.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view showing the main structure of a semiconductor memory device according to an embodiment of the present invention, FIG. 2 is a cross-sectional view showing the structure of a conventional device, and FIG. 3 is a cross-sectional view showing the structure of a conventional device. FIG. 3 is an explanatory diagram illustrating the process required to realize a well structure. 2... Dielectric layer, 4... Storage electrode, 6... Bit line, e... Word line, 7, 8... N-type diffusion layer, 10...P
type semiconductor layer, 13...MOS transistor, 1
2...Groove portion, 20...Semiconductor substrate, 21
...Insulator layer. Name of agent: Patent attorney Toshio Nakao and 1 other name2
figure

Claims (1)

[Claims] a groove formed on a semiconductor substrate of one conductivity type, a diffusion layer of one conductivity type formed on the side and bottom surfaces of the groove, a diffusion layer of an opposite conductivity type formed above the diffusion layer of one conductivity type; formed in the groove and connected to the opposite conductivity type diffusion layer through an insulator layer formed between the conductivity diffusion layer and the opposite conductivity type diffusion layer, and a thin dielectric layer formed on the side and bottom surfaces of the groove portion. A semiconductor memory device comprising a storage electrode for accumulating signal charges, and a read/write MOS transistor formed between the opposite conductivity type diffusion layer and the bit line.