JPS62202288A - Extending system for logical filter - Google Patents

Abstract

PURPOSE:To extend effectively a logical filter by providing a logical filter circuit to execute the filtering of a prescribed size at input data, the adding circuit of the size to add an output and a matching circuit to execute the matching with matching data. CONSTITUTION:When input image data A are inputted to a 3X3 logical filter circuit 1, a circuit 1 obtains a vicinity pattern B from a RAM1-1, for example, 3X3 vicinity pattern. A 3X3 adding circuit 2 adds the vicinity pattern B and obtains an adding result C. As such a result, a signal D, which is an adding result equivalent to the input image data of C, is inputted to a matching circuit 3. Here, in the filter calculation of a purpose which makes the part of '1' of the data A into '1', the matching of the signal D is obtained, the signal D is inputted to a pattern converting circuit 5, 0, 0, 0, 0 are obtained and the logical filter calculation having the function of 5X5 can be executed by a 3X3 logical filter circuit.

Description

[Detailed Description of the Invention] [Summary] This is an expansion method for logic filters, which includes a 3x3 addition circuit and a matching circuit that add the outputs of 3x3 filter circuits, and performs 5x5 logic filter operations. This makes it possible to perform 5×5 filter operations using a 3×3 filter circuit.

[Industrial application field]

The present invention relates to a logical filter expansion method, and more particularly, to a logical filter expansion method that performs a 5×5 logical filter operation using a 3×3 logical filter circuit.

Image processing is actively performed in the field of information processing, and logical filter circuits are used for this image processing. This logic filter generally uses a 3×3 window logic filter circuit and a 5×5 window logic filter circuit.

The 3×3 window and 5×5 window are as shown in FIGS. 4 and 5, and logical operations are performed by inputting the values in each window.

However, the 5x5 logic filter is complicated, and the circuit configuration and constituent elements must be made larger.Therefore, there is a demand for an expansion method for the logic filter that can perform 5x5 operations using a 3x3 logic filter circuit. [Prior Art] Conventionally, there are two methods for performing logical operations: one using wired logic and the other using a RAM table. The former has the disadvantage that the filter contents are fixed, the logic must be changed depending on the purpose of filtering, and the values in the window cannot be changed freely. The latter table method addresses this issue.

On the other hand, in the operation of a 3x3 logical filter, if there is an isolated point A in the input data, as shown in Figure 6 fal, filtering is possible, but if there is an isolated point A in the input data, as shown in Figure 6 (bl), it is possible to filter it. If such a point B exists, filterne is possible, and 5×
This will depend on the calculation of the logical filter in step 5.

[Problems to be Solved by the Invention] As described above, the conventional method has an excellent 5×5 logical filter operation, but has the disadvantage of increasing the capacity of the RA gate in the table format.

The present invention was created in view of these points, and has three
It is an object of the present invention to provide a logical filter calculation method that can perform 3 filter logical calculations using [Changmon] and increase the functionality to 5×5 filter calculations.

[Means to solve the problem] 3x3it that performs 3x3 filtering on input data
The arithmetic circuit of the logic filter is composed of a logic filter circuit, a 3 x 3 adder circuit that adds the outputs of the 3 x 31) logic filter circuits, and a matching circuit that matches the output of the adder circuit and matching data. do.

[Effect]

When the matching circuit performs matching, it converts the matched data to enable calculation of a 5×5 logical filter.

〔Example〕

FIG. 1 is a block diagram of an embodiment of the present invention, in which input image data consisting of one bit is sequentially input to a 3.times.3 logic filter circuit 1 and a delay circuit 4. Connected to the logic filter circuit 1 is a RAM 1-1 that stores 3×3 neighborhood patterns in a table form as shown in FIG.

The output of RAM]-] is input to the 3×3 adder circuit 2. The output of the 3×3 adder circuit 2 is input to the matching circuit 3. The matching circuit 3 is connected to a memory circuit 3-1 that stores matching data. The matching data in which the output of the 3×3 adding circuit 2 matches is outputted from the matching circuit 3 and inputted to the pattern conversion circuit 5.

On the other hand, the input image data input to the delay circuit 4 is
A delay circuit 4 delays the signal so that it is synchronized with the delayed and matched data, and inputs the signal to a pattern conversion circuit 5. The pattern conversion circuit 5 performs the above-described conversion of the matched data at the timing of the input signal, and completes the logic filter operation.

A specific example will be explained using FIG. Input image data A
is input to the 3×3 logic filter circuit 1, 3×3
The logic filter circuit l obtains the neighborhood pattern B shown in FIG. 3 from the 3×3 neighborhood pattern of RAM]-]. 3×
3 Addition circuit 2 adds the neighboring pattern B and obtains the addition result C.
get.

Addition result 107 corresponding to the input image data of addition result C
4.1354.1486.1721 matching circuit 3
Enter. This matching circuit 3 also receives matching data.

In the case of this example, a filter operation is performed for the purpose of converting the logical °1" portion of the input image data to °0", and the matching data is stored in advance as 1074.1354.1486°1721. .Therefore, 1074, 13
54, 148671721 (hereinafter referred to as signal), the signal is input to the pattern conversion circuit 5, and the signal becomes o, o, o, o. functions are maintained.

[9JJ Results of the Invention] As described above, according to the present invention, input data can be changed in one step with an extremely simple configuration, and five
A logic filter operation having a ×5 function is performed by a 3 × 3 logic filter circuit, which is extremely effective in practice.

[Brief explanation of drawings]

Figure 1 is a block diagram of an embodiment of the present invention, Figure 2 is a 3x3
FIG. 3 is a schematic diagram showing a specific example of the present invention; FIG. 4 is a schematic diagram of a 3×3 inlet; FIG. 5 is a schematic diagram of a 5×5 window; The figure is a schematic diagram showing an example of calculation of a logical filter.
a+ is for an isolated point, Figure 6 (bl is for a continuous point. In the figure, 1 is a 3x3 logic filter circuit, and 2 is a 3x3 logic filter circuit.
Reference numeral 3 indicates an adder circuit, reference numeral 3 indicates a matching circuit, and reference numeral 5 indicates a pattern conversion circuit. Engraving of drawings (inside G1.: No changes) tb) Figure 6 Procedures Correction - Correction Inscription March 27, 1985 1985 Patent side No. 189068 2, Name of invention Logic filter expansion method 3. Relationship with the case of the person making the amendment Patent applicant address: 1015 Kamiodanaka, Nakahara-ku, Yozaki City, Kanagawa Prefecture (
522) Name Fujitsu Ltd. Representative Taku Yamamoto 4, agent postal code 21)

Claims (1)

[Claims] 3x filtering of 3x3 on input data
3 logic filter circuit (1) and 3 which adds the outputs of the 3×3 logic filter circuit (1).
It is equipped with a ×3 adder circuit (2) and a matching circuit (3) that compares the output of the adder circuit (2) with matching data, performs pattern conversion when matching is performed, and executes a 3×3 logic filter circuit. A logical filter expansion method characterized in that a 5×5 logical filter operation is performed using the following.