JPS62189760A - High-frequency semiconductor device - Google Patents

Abstract

PURPOSE:To avoid increase of a transmission line loss and facilitate forming a through-hole which reduces the source inductance of an FET by a method wherein the thickness of a semi-insulating GaAs substrate beneath an FET region is made thinner than the thickness of the semi-insulating GaAs substrate beneath micro-strip lines. CONSTITUTION:The recessed part 10 of the back surface of a substrate is formed in the semi-insulating GaAs substrate 1 beneath an FET region and the thickness of the substrate 1 at that part is thin. If the thickness of the semi-insulating GaAs substrate beneath the FET region is 10-20mum, the heat resistance can be reduced and, moreover, as the thickness is small, a through- hole can be formed easily. On the other hand, as the thickness of the semi- insulating GaAs substrate 1 beneath an input side micro-strip line 7 and an output side micro-strip line 8 is as thick as about 100mum, a transmission line loss is not increased. Therefore, a signal can be transmitted to the FET and drawn out of the FET efficiently.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a monolithic microwave IC in which a transistor and a microstrip line are integrated on a semi-insulating semiconductor substrate.

Conventional technology Monolithic microwave ICs (hereinafter referred to as MMICs), in which transistors and strip lines are integrated on a semi-insulating semiconductor substrate, have recently become popular as small-signal analog amplifiers and power devices of around 10Gl-1z. Its uses are expanding greatly. A GaAs substrate is generally used as the semi-insulating substrate, and an MXSFET is formed as a transistor on this GaAs substrate. On the other hand, microstrip lines can be formed by depositing metal on both sides of a semi-insulating GaAt substrate, and MESFK
By combining with T, the input/output impedance becomes 6o.
Ω MMIC is constructed. However, traditional G.I.
LA! ! In MMIC using a substrate, since the semi-insulating GaAs substrate has a uniform thickness, MESFET
If the thickness of the substrate is made thinner for the purpose of lowering the O thermal resistance or making it easier to form through holes, the loss of the strip line increases rapidly, resulting in a decrease in the gain at high frequencies. On the other hand, in order to reduce the loss of the IJ tube line, the board needs to be thicker than a certain level, and in this case, the thickness of the MI
The structure did not satisfy both the MESNET characteristics and the stripline characteristics, such as the increased thermal resistance of the C5FET and the need to dig a deep trench to form a through hole for the FICT source.

FIGS. 4a and 4b are a plan view and a cross-sectional structural view taken along the line A' of the conventional MMrC. The MMIC shown in FIG. 4 is composed of an FIT located in the center and input/output microstrip lines. S, D, and G in FIG. 4a indicate the source terminal, drain terminal, and gate terminal of the FIT, respectively. On the main surface side of the semi-insulating Ga S substrate 1, there are an FIT channel 2, a source region 3. Drain regions 4 are each formed by diffusion. A gate electrode 5 of the FET is arranged on the surface of the channel region 2, and a source electrode 6 is electrically connected to the source region 3, so that the FET operates as a Schottky barrier type FET. The gate terminal G, which is the input of the FIT, is connected to the input side microstrip line 7, and the drain terminal is connected to the output side microstrip line 8, so that the input and output impedance is 6.
converted to oΩ. The input/output microstrip line is composed of a back electrode 9 formed on the back surface of the semi-insulating GaAs substrate 1 and a front electrode formed on the main surface side of the substrate, and efficiently transmits input/output signals. This is what I am trying to do.

Problems to be Solved by the Invention In the conventional high-frequency semiconductor device shown in FIG. 4, semi-insulating G&A! 1 substrate 1 has FET area and micro-
Since the strip line has a uniform thickness over the entire area, semi-insulating GILA is used to lower the FET0 thermal resistance.
! When the thickness of the substrate is reduced to about 20 μm, the transmission line loss of the microstrip line increases rapidly, resulting in signal attenuation and insufficient amplification. On the other hand, when the thickness of the semi-insulating GaAs substrate was increased to about 100 μm in order to reduce the transmission line loss of the micro-strip line, the thermal resistance of the FICT increased and heat generation became a problem. When forming through-holes on a board, please be aware that the thick board can be a major obstacle in the process. As explained above, it is extremely difficult for conventional high-frequency semiconductor devices to satisfy both the characteristics of FICT and the characteristics of microstrip line.

The present invention has been made in view of these points, and provides an excellent MMIC that has a FICT with low thermal resistance and a structure in which through holes can be easily formed, and at the same time has low transmission line loss of microstrip lines. The purpose is to

In order to solve the above-mentioned problem, the present invention reduces the thickness of the semi-insulating GaAs substrate located under the FET area to the semi-insulating GaAs substrate located under the microstrip line. Thinner than the thickness of.

Operation The present invention has the above-described structure, and the semi-insulating GILA5! below the FET region. Since the thickness of the substrate is thin, the thermal resistance of the FET is lowered, and at the same time, it becomes easier to form through holes. or,
Semi-insulating G under micro strip line! LA! ! Since the substrate is thick, transmission line loss can be kept low.

Embodiment FIG. 1 is a plan view and a sectional view taken along the line A' of the high frequency semiconductor device of the present invention. Components in FIG. 1 that are equivalent to those in FIG. 4 are designated with the same reference numbers and symbols. A first embodiment of the present invention, shown in FIG.
A 1° concave portion was formed on the back surface of the substrate to reduce the thickness. The thickness of the semi-insulating GaAs substrate under this FET region is 10~
If it is formed to a thickness of 20 μm, the thermal resistance can be lowered, and since the thickness is thin, it will not become an obstacle when forming through holes. On the other hand, the semi-insulating G where the input side microstrip line 7 and the output side microstrip line 8 are located
Since the aAg substrate 1 is thick, approximately 100 μm, transmission line loss does not increase. Therefore, the signal fc can be efficiently
As explained above, according to the present invention, a recess 10 on the back surface of the semi-insulating GaAg substrate 1 is provided on the back surface of the portion where the WET is located. At the same time as reducing the thickness of the board,
Semi-insulating GaAs on which microstrip lines are located
Since the substrate is thicker than the substrate thickness under the FET area, it has lower thermal resistance for the FIT and prevents deterioration of mutual conductance due to heat generation. Compared to a strip line, the transmission line loss can be kept low, making it possible to achieve both characteristics.

FIG. 2 is a plan view and a sectional structural view showing a second implementation row of the high frequency semiconductor device of the present invention. Similar to the first embodiment of the present invention shown in FIG.
Only the part where ET is located is thinner, but it is semi-insulating G.
The entire aAs substrate is grown on a silicon semiconductor substrate 11 at a ratio of 1/i. The silicon semiconductor substrate 11 can be used as the back electrode if it contains impurities at a high concentration and has a resistance of about 0.1 Ω1. Even with such a configuration, a low thermal resistance of the FET and a low-loss microstrip line can be realized at the same time.

FIG. 3 is a plan view and a sectional structural view showing a third implementation row of the high frequency semiconductor device of the present invention. Figure 3 shows semi-insulating e
By forming a gold plating layer 12 with a thickness of 10 μm or more on the back surface of the aAs substrate and filling the recess 10 on the back surface of the substrate with the gold plating layer, bonding of the chip to a package, etc. is facilitated, and holes are formed in the recess 1o on the back surface of the substrate. This is to prevent

Although the present invention has been described in terms of a semi-insulating GaAs substrate, the thickness of the semi-insulating substrate in the transistor part is half the thickness of the microstrip line part even in the case of other semiconductor materials. It goes without saying that the same effect can be obtained if the thickness is thinner than the thickness of the insulating substrate.

Effects of the Invention As described above, the present invention provides the following effects.

(1) Since the thickness of the semi-insulating substrate located under the FET area is thin, thermal resistance can be kept low, and at the same time,
The thickness of the semi-insulating substrate under the micro-strip line area is kept above a certain level, so the increase in transmission line loss is minimized.

(2) Since the thickness of the semi-insulating substrate located under the FET region is thin, it is easy to form through holes for the purpose of lowering the source inductance of the FIT.

[Brief explanation of drawings]

FIGS. 1, 2, and 3 are plan and cross-sectional structural views showing implementation rows of the high-frequency semiconductor device of the present invention, and FIG. 4 is a plan view and cross-sectional structural view showing a conventional high-frequency semiconductor device. 1... Semi-insulating GaAs substrate, 2...
Channel, 3... Source area, 4...
・Drain region, 5...Gate electrode, 7...
...Input side micro strip line, 8...
・Output ([111 Micro Street, -) Buwataji-9・
... Back electrode, 1o... Recessed part on the back surface of the substrate,
11... Silicon semiconductor substrate, 12...
・Gold plated layer. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 Figure 3 Figure 4

Claims (3)

[Claims] (1) In a high-frequency monolithic semiconductor device in which a transistor region and a microstrip line region are integrated into a first semi-insulating semiconductor substrate, the thickness of the semi-insulating semiconductor substrate located below the transistor region. is thinner than the thickness of a semi-insulating semiconductor substrate located under a microstrip line. (2) The high frequency semiconductor device according to claim 1, wherein the semi-insulating semiconductor substrate is formed on a conductive silicon semiconductor substrate. (3) The high frequency semiconductor device according to claim 1, further comprising a gold plating layer having a thickness of 10 μm or more on the back surface of a semi-insulating semiconductor substrate.