JPS62183214A - Peak detection circuit - Google Patents

Abstract

PURPOSE:To detect the peak of an input signal at its substantial peak position by comparing an input with a reference voltage and using an AND gate output so as to detect the peak point below the reference voltage. CONSTITUTION:An input signal A shown in waveform (a) is inputted to a differential circuit 1, where a differentiation output B is obtained, and it is inputted to a zero cross comparator circuit 2, and the output D of a rectangular wave front edge pulse circuit 3 receiving the zero cross comparator output C represents an output shown in pulse waveform (d) at all peak points of the input signal A and is inputted to an AND circuit 6. On the other hand, the output E of a comparator circuit 4 being the result of comparison between a reference voltage VREF of a prescribed level and the input signal A is inputted to the AND circuit 6 as an inverted output shown in waveform (f). When two input signals D, F are at H level in respective waveforms (d, f), the result is extracted as the output G of the circuit 6 to detect peak points of the analog input signal A at the prescribed level of the reference voltage VREF or below.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a peak value detection circuit for analog signals.

[Conventional technology]

Traditionally, peak detection circuits have been obtained through analog input signal total differentiator circuits and zero-cross comparator circuits.

[Problem that the invention seeks to solve]

However, a circuit with such a configuration has a problem in that a peak may be detected at a portion other than the original peak position of the input signal.

[Means for solving problems]

In order to eliminate the drawbacks of the above-mentioned conventional example, the present invention comprises a circuit that compares an input with a reference voltage and detects a peak point below the reference voltage using an AND gate output.

〔Example〕

Hereinafter, one embodiment of the present invention will be described based on all the drawings.

First, the configuration will be described using the schematic diagram shown in FIG.

A circuit sequentially connected from a differentiating circuit 1 to which an analog input signal Ae is applied to a zero cross comparator circuit 2 and a square wave leading edge pulse generating circuit 3'1AND circuit 6; and a reference tEEVREF having a predetermined level with respect to the input signal A; This peak detection circuit is composed of a comparator circuit 4 which inputs the signal, and a circuit connected to the AND circuit 6 via an inverter 5.

Next, the operation will be explained while also referring to the time chart shown in FIG.

The human input signal A of waveform a is inputted to the differentiator circuit 1 and appears as the differential output B of the waveform A, and the zero cross comparator circuit 2
is input. The output of the square wave leading edge pulse circuit 3 of the zero cross comparator output C, which has become a square wave C, is the pulse waveform d at all peak points of the input signal A.
, and is input to the AND circuit 6.

On the other hand, the reference voltage EEVREF at a predetermined level and the input signal A<! :'i The compared output E of the comparator circuit 4 is
After passing through the inverter 5, the inverted signal F of the output becomes a waveform f and is input to the AND circuit 6.

Therefore, as shown in FIG. 2, I-t low level, H=
) If the waveform is a high level, the AND circuit 6 takes the logical product according to the following rules, so the two input signals are
are the respective waveforms d.

If both f are H, that is, the pulse waveform d
Since the waveform g has two pulses in the center, it is taken out as the output G of the circuit 6, and the peak point is detected below a certain level reference voltage VREF of the analog input signal A, and the voltage VREF Peak values are not detected in the above peak portions.

〔Effect of the invention〕

As explained above, according to the present invention, the analog input signal is set to a certain predetermined level. Since the circuit configuration is used for comparison with the reference voltage, it is possible to extract only the peak points below the reference voltage, and it is possible to obtain the effect that peak detection can be performed only at necessary peak points.

[Brief explanation of drawings]

FIG. 1 is a peak detection circuit diagram according to an embodiment of the present invention;
FIG. 2 is also a time chart of each signal. A...Analog human input signal VREF...Reference voltage 1...Differentiating circuit 2...Zero cross comparator circuit 3...
...Square wave leading edge pulse generation circuit 4 ...Comparator circuit 6 ...AND circuit $3 amount I Official 4io Time Child Yard Figure 2

Claims (1)

[Claims] A differentiator circuit, a zero cross comparator circuit, and a square wave leading edge pulse generator circuit to which an analog input signal is applied are connected in sequence and led to an AND circuit, and the analog input signal is compared with a reference voltage at a predetermined level. The inverted output from the comparator circuit is led to the AND circuit, and is logically ANDed with the output of the square wave leading edge pulse generating circuit to detect a peak below a predetermined level for the analog input signal. A peak detection circuit characterized by having a configuration capable of detecting only points.