JPS62177940A - Semiconductor logic integrated circuit device - Google Patents

Semiconductor logic integrated circuit device

Info

Publication number
JPS62177940A
JPS62177940A JP1780786A JP1780786A JPS62177940A JP S62177940 A JPS62177940 A JP S62177940A JP 1780786 A JP1780786 A JP 1780786A JP 1780786 A JP1780786 A JP 1780786A JP S62177940 A JPS62177940 A JP S62177940A
Authority
JP
Grant status
Application
Patent type
Prior art keywords
wirings
cell
layer
wiring
disposed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1780786A
Inventor
Takashi Saigo
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118Masterslice integrated circuits
    • H01L27/11803Masterslice integrated circuits using field effect technology
    • H01L27/11807CMOS gate arrays

Abstract

PURPOSE:To improve the degree of freedom of wirings by crosswise making a first wiring in wirings in a cell travel and using three-layer metallic wirings as wirings among cells while also forming wiring regions among partial cells on a logic cell row. CONSTITUTION:A power line 211, a ground line 212, an output line 213 and input lines 214, 215 are disposed to a first layer wiring in a fundamental cell in which N and P channel MOS transistors Q1-Q4 at every two shaped onto a chip substrate are disposed, and input/output terminals 221-223 are formed by two-layer wirings, limited to a cell central section, thus constituting an NAND gate as a logic cell. Each logic cell 1211-1214, 1221-1224 is connected by metallic wirings consisting of first layer wirings 14 arranged on a wiring track for an exclusive wiring region 13 traveling in the same direction as logic cell rows 121, 122, second layer wirings 15 disposed in the direction orthogonal to the wirings 14, and third layer wirings 16 partially arranged in the direction of the arrangement of the cell rows 121, 122 on the cell rows 121, 122 and disposed in the same manner as the wirings 14.
JP1780786A 1986-01-31 1986-01-31 Semiconductor logic integrated circuit device Pending JPS62177940A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1780786A JPS62177940A (en) 1986-01-31 1986-01-31 Semiconductor logic integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1780786A JPS62177940A (en) 1986-01-31 1986-01-31 Semiconductor logic integrated circuit device

Publications (1)

Publication Number Publication Date
JPS62177940A true true JPS62177940A (en) 1987-08-04

Family

ID=11953999

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1780786A Pending JPS62177940A (en) 1986-01-31 1986-01-31 Semiconductor logic integrated circuit device

Country Status (1)

Country Link
JP (1) JPS62177940A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5111271A (en) * 1989-06-26 1992-05-05 Kabushiki Kaisha Toshiba Semiconductor device using standard cell system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5111271A (en) * 1989-06-26 1992-05-05 Kabushiki Kaisha Toshiba Semiconductor device using standard cell system

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