JPS62175671A - Logic analyzer - Google Patents

Abstract

PURPOSE:To enable measuring conditions to be freely changed even in a measurement and optimum display conditions to be obtained by setting a logic analyzer to a repetitive measurement mode. CONSTITUTION:A logic analyzer is constituted by means for making a data memory 5 repetitively execute the fetch of timing waveform data, key input task executing means 8B for making a key input task be executed apart from a measuring task in the condition wherein repetitively measuring means 8A is operated and a clock setting register 6A for defining the clock pulse generating frequency of a sampling pulse generator 6. In the condition wherein the means 8A is operated, the means 8B performs a parallel operation independent of a measuring task. For this reason, by inputting measuring conditions from a keyboard 12 even in a measurement, a controller 8 can fetch the measuring conditions. The controller 8 transfers the inputted measuring condition to a register 6A provided in the generator 6 and rewrites the subsequent measuring conditions.

Description

DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention relates to a logic analyzer used for analyzing the operation of a digital circuit.

"Conventional technology" FIG. 3 shows the configuration of a conventional logic analyzer.

In FIG. 3, 1 indicates an object to be measured. The object to be measured 1 corresponds to various digital circuits.

Digital waveform data of each part of the object to be measured 1 is taken into the level conversion circuit 3 through the input terminal group 2. The input terminal group 2 may have, for example, 8 channels to 16 channels, and in some cases up to 100 channels.

The level converter 3 thus defines the digital waveform data of a plurality of channels into a signal having a level suitable for being taken in, and writes the digital waveform data into the data memory 5 via the buffer memory 4.

Reference numeral 6 indicates a clock pulse generator, and the buffer memory 4 and the address counter 7 are driven by the clock pulse PC output from the clock pulse generator 6, and the data memory 5 is accessed by the address signal generated by the address counter 7. Writing is performed.

8 indicates a controller. This control group 8 is constituted by, for example, a microcomputer, and is connected to the data memory 5, address counter 7, etc. via a path line 9. The data memory 5 is controlled to be switched between a write state and a read state by this controller 8. The address counter 7 is also given the start and end addresses for writing or the start and end addresses for read from the controller 8.

The digital waveform data taken into the data memory 5 is read out under the control of the controller 8 and transferred to the display 11. As shown in FIG. 4, the display 11 displays digital waveform data A and B for each channel at 5.

Display C and D.

Reference numeral 12 indicates a keyboard attached to the controller 8.

Measurement conditions and the like are input to the controller 8 using the keyboard 12, and desired conditions are set.

The measurement conditions include, for example, the data acquisition speed. The data acquisition speed is determined by the clock pulse generator 6.
This is done by switching the clock frequency of the Other measurement conditions include setting the delay amount of the delay counter 13 and setting the detection conditions of the trigger detection circuit 14 shown in the figure. The trigger detection circuit 14 monitors input waveform data,
A detection signal is output when the input waveform data matches the set conditions. For example, when the signals of all channels become L logic, ■ (logic), or match various other signals, a detection signal is output, and this detection signal is used as, for example, a write start command or a write stop command. Make use of it.

The delay counter 13 is provided so that the time from when this detection signal is output until the start or stop of writing can be delayed by an arbitrary period of time.

FIG. 5 shows a flow chart outlining the operation of the controller 8. As shown in the figure, at the start of measurement, measurement conditions are input from the keyboard in step (2), measurement is started in step (2) when the measurement conditions are complete, and measurement is executed in step (2). Waveform data is stored in data memory 5 by measurement execution.
The result is displayed on the display 11. Step■
examines the displayed waveform and analyzes the data. In step (2), an inquiry is made as to whether or not there is a need for measurement again.

If there is a need for measurement based on the input from the keyboard 12, the process returns to step (2) and measurement is performed again. If it is not necessary to measure again, skip step ① and finish the measurement.

"Problems to be Solved by the Invention" In the conventional logic analyzer, in order to change the measurement conditions, it is necessary to end the measurement, restart it, and execute step (3) of setting the measurement conditions.

Therefore, when changing the measurement conditions, there is a drawback that it takes time to display the measurement results under the new conditions from the state in which the previous measurement results were displayed.

For example, if timing waveform data is acquired at a certain lock pulse period and the results are displayed, but the clock pulse period is too fast and only a portion of the timing waveform data can be displayed, conventionally, the measurement mode is temporarily terminated. , I activated the measurement mode again, executed step (3), changed the measurement condition settings, and then measured again. Therefore, it is necessary to repeat the process several times before obtaining data in the optimum state for timing analysis.

Another drawback is that it is not possible to adopt a measurement method in which measurements (data acquisition) are repeatedly performed while sequentially shifting trigger conditions in order to successfully capture, for example, transient phenomena that occur intermittently.

SUMMARY OF THE INVENTION An object of the present invention is to provide a logic analyzer that can freely change measurement conditions even during measurement and easily obtain an optimal display state.

"Means for Solving the Problem" The present invention includes a data memory for capturing timing waveform data, a display device for displaying the timing waveform data captured in the data memory, and a display device for displaying the timing waveform data captured in the data memory. A logic device consisting of a controller that controls the complex data transfer, a keyboard that inputs measurement conditions, etc. to this controller, and a clock generator that generates a clock to import timing waveform data into the data memory. In the analyzer, a means for repeatedly loading timing waveform data into a data memory, a key input task execution means for executing a key input task separately from a measurement task while the repetitive measurement means is operating, and a clock generation means. This configuration includes a clock setting register that defines the clock pulse generation frequency of the device.

According to the configuration of the present invention, while the repeat measurement means is operating, the key input task execution means operates in parallel with the measurement task. Therefore, even during measurement, by inputting the measurement conditions from the keyboard, the measurement conditions can be imported into the controller. The controller transfers the input measurement conditions to a condition setting register provided in the clock generator, and rewrites the next measurement conditions.

As described above, according to the present invention, measurement conditions can be changed at least regarding the frequency of the clock pulse in the repeated measurement mode.

Therefore, it is convenient to be able to view the displayed results and sequentially shift the measurement conditions to obtain the optimal display condition for timing analysis.

"Embodiment" FIG. 1 shows an embodiment of the present invention. In Figure 1, 1
is the digital circuit device to be tested, 2 is the input terminal group of the logic analyzer, 3 is the level converter, 4 is the buffer memory, 5 is the data memory, 6 is the clock pulse generator, 7 is the address signal to the data memory 5 8 is a controller, 9 is a pass line, 11 is a display, 12 is a keyboard, 13 is a delay counter, 1
Reference numeral 4 indicates a trigger detection circuit, which is the same as the conventional one.

In this invention, the controller 8 includes repeat measurement execution means 8A.
and key input task execution means 8B. The repeated measurement execution means 8A and the key input task execution means 8B can be constituted by a microcomputer forming the controller 8 and a program for operating this microcomputer.

Repeated measurement execution means 8A and key input task execution means 8
An overview of the programs that make up B is shown in Figure 2. In FIG. 2, steps ① to ① constitute the measurement task. Among these steps, step (2) and step (2) constitute the repeated measurement execution means 8A. In steps (2) and (2), it is determined whether a repeat flag exists or not, and if the repeat flag is on, steps (2) to (2) are repeatedly executed. At the same time, steps (1) to (2) constituting the key input task are executed in parallel.

In other words, in the measurement task, step ■ encourages key human power. In step (3), input measurement conditions from the keyboard 4. In step (2), it is determined whether or not repeated measurement is designated from the measurement condition settings based on the presence or absence of a repeat flag. If there is no repeat flag, jump to step (2), take in the timing waveform data once, display the result, and end.

If the repeat flag exists, execute step (■).

In step (2), the key input task is activated and input from the keyboard 4 is accepted. In this state, when the measurement conditions to be set for the next measurement are inputted from the keyboard 4, the measurement conditions are written into the setting register in step (3). This writing is executed upon detecting that the previous timing waveform data acquisition has been completed. This detection can be performed using a stop signal output from the trigger detection circuit 14.

Step ■ determines whether there is an input to end the measurement,
If there is no input to end the measurement, return to step ① and repeat the execution of the key input task. If there is an input to end the measurement, use Step ■ to change the repeat flag of the measurement task to nothing and end the measurement.

In the present invention, a repeat measurement execution means 8A and a key input task execution means 8B which operate in this manner are provided, and at least the clock pulse generator 6 is provided with a setting register 6A.

In the illustrated example, the delay counter 13 is set to the delay setting register 13.
A, a trigger condition setting register 14A is provided in the trigger detection circuit 14, and a threshold voltage generator 15 that provides a reference voltage for determining the level of signal acquisition to the level converter 3; 1
An example is shown in which a threshold voltage setting register 15A is provided to set the threshold voltage outputted from 5.

In this way, by attaching the setting registers 6A, 13A, 14N, and 15A to each circuit 6, 13, 14, and 15, it is possible to control not only the frequency of the clock pulse but also the trigger detection condition and the operation of the address counter 7, etc. from trigger detection. The delay time until stopping and the threshold voltage value for determining whether to take in the timing waveform data as H logic or L logic can be written into each of these setting registers by the key input task.

Therefore, according to the embodiment shown in FIG. 1, a plurality of measurement conditions other than the clock pulse frequency can be set and changed.

"Operations and Effects of the Invention" As explained above, according to the present invention, by setting the repeat measurement mode, at least the frequency of the clock pulse that determines the speed at which timing waveform data is taken into the data memory 5 can be used for the next measurement even during measurement. The clock frequency can be input from the keyboard and its value written to the configuration register 6A by the key input task.

Therefore, if the repeat measurement mode is set, the frequency of the clock pulse can be sequentially changed while repeating the measurement.

Therefore, it is possible to observe how the measurement results change in response to changes in the measurement conditions, and to set the optimum state in a short time.

As a result, an easy-to-use logic analyzer can be provided.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a flowchart for explaining the configuration and operation of the main parts of the present invention, and FIG. 3 is for explaining the configuration of a conventional logic analyzer. FIG. 4 is a front view showing an example of the display results of the logic analyzer, and FIG. 5 is a flowchart for explaining the operation of the conventional logic analyzer. 1: Digital circuit under test, 2: Input terminal group, 3 two-level f conversion! , 4: buffer memory, 5: data memory,
6: Clock pulse generator, 6A: Clock setting register, 7: Address counter, 8: Controller, 8N: Repeated measurement execution means, 8B: Key input task execution means, 9:
Bus line, 11: Display, 12: Keyboard, 13
: Delay counter, 13N: Delay setting register, 14A:
Trigger condition setting register, 15A: Threshold voltage setting register.

Claims (1)

[Claims] (1) A: at least a data memory, an address counter that provides read and write address signals to this data memory, a clock pulse generator that provides clock pulses to these data memories and the address counter, and a clock pulse generator that provides clock pulses to the data memory and the address counter; In a logic analyzer comprising a display for displaying data, a control unit for controlling the transfer of data from the data memory to the display, and a keyboard for inputting measurement conditions, B. the clock pulse generation; a clock setting register that is attached to the device and controls the frequency of the clock output from the clock pulse generator; a means for repeatedly loading timing waveform data into the data memory; A logic analyzer comprising: key input task execution means for executing a key input task separately from a measurement task.