JPS6217416B2 - - Google Patents

Info

Publication number
JPS6217416B2
JPS6217416B2 JP8079582A JP8079582A JPS6217416B2 JP S6217416 B2 JPS6217416 B2 JP S6217416B2 JP 8079582 A JP8079582 A JP 8079582A JP 8079582 A JP8079582 A JP 8079582A JP S6217416 B2 JPS6217416 B2 JP S6217416B2
Authority
JP
Japan
Prior art keywords
switch
section
power supply
disconnection
switches
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP8079582A
Other languages
Japanese (ja)
Other versions
JPS58196722A (en
Inventor
Yasuo Furukawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advantest Corp
Original Assignee
Advantest Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advantest Corp filed Critical Advantest Corp
Priority to JP8079582A priority Critical patent/JPS58196722A/en
Publication of JPS58196722A publication Critical patent/JPS58196722A/en
Publication of JPS6217416B2 publication Critical patent/JPS6217416B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66Digital/analogue converters
    • H03M1/74Simultaneous conversion
    • H03M1/78Simultaneous conversion using ladder network
    • H03M1/785Simultaneous conversion using ladder network using resistors, i.e. R-2R ladders

Description

【発明の詳細な説明】 この発明は抵抗ラダネツトワークを用いてデジ
タル値をアナログ値に変換するDA変換器に関
し、特にその構成抵抗素子のバラツキによる影響
を小にしようとするものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a DA converter that converts a digital value into an analog value using a resistance ladder network, and is particularly intended to reduce the influence of variations in its constituent resistance elements.

〔従来技術〕[Prior art]

第1図は従来のラダネツトワークを用いた電流
モード形DA変換器を示す。直列抵抗器11とジ
ヤント抵抗器12とよりなるセクシヨンL1L2
……Lnを直列に接続したラダネツトワーク13
が設けられ、ラダネツトワーク13の一端は定電
流源14に接続され、他端は抵抗器15を通じて
定電流源14の他端である共通電位点に接続され
る。ラダネツトワーク13の各セクシヨンL1
Lnのシヤント抵抗器12の他端はそれぞれ切替
スイツチS1〜Snの可動接点に接続される。切替
スイツチS1〜Snの各一方の固定接点は共通電位
点に接続され、各他方の固定接点は演算増幅器1
6の反転入力側に接続される。演算増幅器16の
出力側及びその反転入力側間に帰還抵抗器17が
接続され、演算増幅器16の非反転入力側は共通
電位点に接続される。
Figure 1 shows a current mode DA converter using a conventional RADAR network. Section L 1 L 2 consisting of series resistor 11 and giant resistor 12...
...Rada network 13 with Ln connected in series
One end of the ladder network 13 is connected to a constant current source 14, and the other end is connected to the other end of the constant current source 14, a common potential point, through a resistor 15. Each section of Radha Network 13 L 1 ~
The other ends of the shunt resistors 12 Ln are connected to the movable contacts of the changeover switches S 1 to Sn, respectively. One fixed contact of each of the changeover switches S 1 to Sn is connected to a common potential point, and the other fixed contact of each switch is connected to the operational amplifier 1.
Connected to the inverting input side of 6. A feedback resistor 17 is connected between the output side of the operational amplifier 16 and its inverting input side, and the non-inverting input side of the operational amplifier 16 is connected to a common potential point.

ラダネツトワーク13の各直列抵抗器11、抵
抗器15,17の各抵抗値はR、ラダネツトワー
ク13の各シヤント抵抗器12の抵抗値は2Rと
されてある。切替スイツチS1〜Snは2進入力デ
ジタル値の各対応ビツトで制御され、そのビツト
が“0”の場合は共通電位点、“1”の場合は演
算増幅器16の反転入力側に接続される。nビツ
トの入力デジタル値の最上位ビツトMSBにより
切替スイツチS1が、最下位ビツトLSBにより切替
スイツチSnが制御される。セクシヨンL1〜Lnの
各シヤント抵抗器12に流れる電流i1〜inは2進
重みが付けられたものとなる。この場合、高い精
度の変換精度を得るには抵抗器11,12の各抵
抗値の精度を高いものとする必要がある。
The resistance value of each series resistor 11, resistor 15, 17 in the RADAN network 13 is set to R, and the resistance value of each shunt resistor 12 in the RADAN network 13 is set to 2R. The changeover switches S1 to Sn are controlled by each corresponding bit of the binary input digital value, and when the bit is "0", they are connected to the common potential point, and when the bit is "1", they are connected to the inverting input side of the operational amplifier 16. . The most significant bit MSB of the n-bit input digital value controls the changeover switch S1 , and the least significant bit LSB controls the changeover switch Sn. The currents i 1 -in flowing through each shunt resistor 12 of sections L 1 -Ln are binary weighted. In this case, in order to obtain high conversion accuracy, it is necessary to make each resistance value of the resistors 11 and 12 highly accurate.

〔発明の概要〕[Summary of the invention]

この発明の目的はラダネツトワークのセクシヨ
ンを入力デジタル値の変化と比較して充分高速に
入れかえることにより抵抗値のバラツキを平均化
して高精度の変換出力を得ることができるDA変
換器を提供することにある。
The purpose of this invention is to provide a DA converter that can average out variations in resistance values and obtain highly accurate conversion outputs by replacing sections of a RADAR network at a sufficiently high speed compared to changes in input digital values. There is a particular thing.

この発明の一例によれば直列抵抗器、シヤント
抵抗器よりなるN個のセクシヨンが順次、切離ス
イツチを介してリング状に接続され、各セクシヨ
ンの直列抵抗器と並列に短絡スイツチが接続さ
れ、各シヤント抵抗器の他端に切替スイツチの可
動接点がそれぞれ接続され、これら可動接点の一
方の固定接点は共通電位点に接続され、他方の固
定接点は電流モード形の場合は共通の出力端子に
接続され、電圧モード形の場合は共通の電源に接
続される。また各セクシヨンの接続点は電流モー
ド形の場合は給電スイツチを通じて定電流源に接
続され、電圧モード形の場合は出力スイツチを通
じて共通の出力端子に接続される。
According to an example of the present invention, N sections consisting of series resistors and shunt resistors are sequentially connected in a ring shape through disconnection switches, and a shorting switch is connected in parallel with the series resistor of each section, A movable contact of a changeover switch is connected to the other end of each shunt resistor, and one fixed contact of these movable contacts is connected to a common potential point, and the other fixed contact is connected to a common output terminal in the case of a current mode type. In the case of voltage mode type, it is connected to a common power supply. Further, the connection point of each section is connected to a constant current source through a power supply switch in the case of a current mode type, and to a common output terminal through an output switch in the case of a voltage mode type.

切離スイツチの1つがオフにされ、その切離ス
イツチの一方側に接続される給電スイツチ(又は
出力スイツチ)はオンにされ、他方側に接続され
る切替スイツチは共通電位点に接続され、その切
替スイツチが共通電位点に接続された側の隣接す
るセクシヨンの短絡スイツチがオンにされる。更
に入力デジタル値の各ビツトと対応して、各切替
スイツチが何れかに切替え接続される。このよう
な各スイツチの設定状態を、上記セクシヨンのリ
ング上の相対位置を保持して切離スイツチを一定
周期で順次オフにすると共に他のスイツチの制御
をスイツチ制御部で行う。このスイツチ制御によ
りセクシヨンの位置が順次入れ替えられて、各セ
クシヨン間のバラツキが平均化される。
One of the disconnection switches is turned off, the feed switch (or output switch) connected to one side of the disconnection switch is turned on, and the transfer switch connected to the other side is connected to a common potential point and its The shorting switches of the adjacent sections on the side whose changeover switches are connected to the common potential point are turned on. Furthermore, corresponding to each bit of the input digital value, each changeover switch is selectively connected. The setting state of each switch is maintained by maintaining the relative position of the section on the ring, turning off the disconnection switch one after another at a constant cycle, and controlling the other switches by a switch control section. By this switch control, the positions of the sections are sequentially changed, and the variations between the sections are averaged out.

〔第1実施例〕 第2図はこの発明を電流モード形に適用した一
例を示し、抵抗値Rの抵抗器11の8個が切離ス
イツチS9〜S16の各1個づつを順次介してリング
状に接続され、各切離スイツチと抵抗器11の一
方の接続点に抵抗値2Rの抵抗器12の一端がそ
れぞれ接続されて各1個の抵抗器11,12のセ
クシヨンL1〜L8がリング状に接続されたラダネ
ツトワークが構成される。各抵抗器11にはそれ
ぞれ短絡スイツチS17〜S24が各1個ずつ並列に接
続される。各セクシヨンの接続点における抵抗器
11及び切離スイツチの接続点はそれぞれ給電ス
イツチS1〜S8を通じて定電流源14に接続され
る。各抵抗器12の他端は切替スイツチS25〜S32
の各可動接点にそれぞれ接続され、各切替スイツ
チS25〜S32の一方の固定接点は共通電位点に接続
され、各他方の固定接点は出力端子18に接続さ
れる。
[First Embodiment] FIG. 2 shows an example in which the present invention is applied to a current mode type, in which eight resistors 11 having a resistance value R are sequentially connected to one each of disconnection switches S9 to S16 . They are connected in a ring shape, and one end of a resistor 12 with a resistance value of 2R is connected to one connection point between each disconnection switch and the resistor 11 . A Rada network is constructed in which 8 are connected in a ring shape. Each resistor 11 is connected in parallel with one shorting switch S 17 to S 24 . The connection points of the resistor 11 and the disconnection switch at the connection points of each section are connected to a constant current source 14 through power supply switches S1 to S8 , respectively. The other end of each resistor 12 is a changeover switch S 25 to S 32
One fixed contact of each of the changeover switches S 25 to S 32 is connected to a common potential point, and the other fixed contact of each switch S 25 to S 32 is connected to the output terminal 18 .

1つの切離スイツチS16がオフとされ、そのオ
フとされた切離スイツチS16の一端の給電スイツ
チS1はオンとされ、他端の切替スイツチS32は共
通電位点に接続される。オフとされた切離スイツ
チS16の切替スイツチS32を共通電位点に接続した
側の隣接セクシヨンの短絡スイツチS23とはオン
にされる。1つの切離スイツチS16をオフにした
時に、セクシヨンL1〜L7の縦続接続よりなるラ
ダネツトワークが構成され、その一端のセクシヨ
ンL1は電源14に接続され、他端のセクシヨン
L7では抵抗器11が短絡スイツチS23により短絡
され、セクシヨンL8の抵抗器12中の抵抗値R
とセクシヨンL7の抵抗器12とによりラダネツ
トワークとしての1つのセクシヨンを構成し、セ
クシヨンL8の抵抗器12中の抵抗値Rで終端さ
れる。
One disconnection switch S16 is turned off, the power supply switch S1 at one end of the disconnection switch S16 that has been turned off is turned on, and the changeover switch S32 at the other end is connected to a common potential point. The short-circuit switch S 23 of the adjacent section on the side connected to the common potential point is turned on with the changeover switch S 32 of the disconnection switch S 16 which has been turned off. When one disconnection switch S 16 is turned off, a ladder network consisting of the cascade connections of sections L 1 to L 7 is formed, of which section L 1 at one end is connected to the power supply 14 and section at the other end is connected to the power supply 14.
In L 7 the resistor 11 is shorted by the shorting switch S 23 and the resistance R in the resistor 12 of section L 8
and the resistor 12 of section L7 constitute one section as a ladder network, and is terminated at the resistance value R in the resistor 12 of section L8.

1つの切離スイツチS16がオフの時においては
ラダネツトワークの電源14側、つまりセクシヨ
ンL1の切替スイツチS25が入力デジタル値の最上
位ビツトで制御され、入力デジタル値の最下位ビ
ツトで終段のセクシヨンL7の切替スイツチS31
制御される。同様にして入力デジタル値の各対応
ビツトに応じてセクシヨンL2〜L6の各切替スイ
ツチS26〜S30が制御される。例えば入力デジタル
値が101000の場合は切替スイツチS25,S27が出力
端子10側とされる。オフとする切離スイツチを
順次切替えるに従い、7セクシヨンのラダネツト
ワークが順次循環されるに従つて各切替スイツチ
中の出力端子側とされるものもそのリング上の切
離スイツチに対する相対的位置を保持して切替え
られ、同様にオンとされる給電スイツチの共通電
位点側とされる切替スイツチもオフとされる切離
スイツチに対する相対的位置を保持して切替えら
れる。第3図に第2図におけるスイツチ制御のタ
イムチヤートの例を、入力デジタル値が101000の
場合について示す。
When one disconnection switch S16 is off, the changeover switch S25 on the power supply 14 side of the Rada network, that is, section L1 , is controlled by the most significant bit of the input digital value, and is controlled by the least significant bit of the input digital value. The changeover switch S31 of the final stage section L7 is controlled. Similarly, the changeover switches S26 to S30 of sections L2 to L6 are controlled in accordance with each corresponding bit of the input digital value. For example, when the input digital value is 101000, the changeover switches S 25 and S 27 are set to the output terminal 10 side. As the disconnection switches to be turned off are sequentially switched, as the seven sections of the radar network are sequentially circulated, the output terminal side of each changeover switch also changes its position relative to the disconnection switch on the ring. The changeover switch, which is held and switched, and which is placed on the common potential point side of the power supply switch that is similarly turned on, is also switched while maintaining its relative position with respect to the disconnection switch that is turned off. FIG. 3 shows an example of a time chart of the switch control in FIG. 2 when the input digital value is 101,000.

〔スイツチ制御部〕[Switch control section]

このようにスイツチを制御するスイツチ制御部
の例を第4図に示す。制御部はスイツチS1〜S32
を制御する定制御部21と、切替スイツチS25
S32を制御する出力制御部22とからなり、定制
御部21は例えばD形フリツプフロツプFF1
FF8が縦続接続され、その終段のフリツプフロツ
プFF8のQ出力が初段のフリツプフロツプFF1
データ端子Dに帰還され、初段のフリツプフロツ
プFF1のプリセツトデータ端子Aには高レベル
“1”が与えられ、他のフリツプフロツプFF2
FF8のプリセツトデータ端子Aにはそれぞれ低レ
ベル“0”が与えられ、フリツプフロツプFF1
FF8のクロツク端子に、端子23からクロツクが
与えられるごとにシフト動作を行う循環形シフト
レジスタとされている。
An example of a switch control section that controls the switch in this manner is shown in FIG. The control section is switch S 1 ~ S 32
a constant control section 21 that controls the changeover switch S25 to
The constant control section 21 includes, for example, a D-type flip-flop FF 1 to
FF 8 are connected in cascade, and the Q output of the final stage flip-flop FF 8 is fed back to the data terminal D of the first stage flip-flop FF 1 , and a high level "1" is applied to the preset data terminal A of the first stage flip-flop FF 1 . given other flip-flops FF 2 ~
A low level "0" is given to the preset data terminals A of FF 8 , respectively, and flip-flops FF 1 to
It is a circular shift register that performs a shift operation every time a clock is applied from the terminal 23 to the clock terminal of FF8 .

第3図Aに示すようにロード端子24に時点t1
でロード指令がフリツプフロツプFF1〜FF8の各
プリセツト端子Pに与えられると、フリツプフロ
ツプFF1に“1”がその他に“0”がプリセツト
され、このデータパターン“100……0”が第3
図Bに示す端子23のクロツクごとにシフトし、
フリツプフロツプFF1〜FF8の各Q出力Q1〜Q8
それぞれ第3図C〜Jに示すように変化する。こ
のクロツクの周期はTとされ、フリツプフロツプ
FF1〜FF4の各Q出力Q1〜Q8の出力でそれぞれ第
2図中の給電スイツチS1〜S8,S23,S24,S17
S22が制御され、フリツプフロツプFF1〜FF8の各
出力により第3図中の切離スイツチ
S16,S9〜S15、切替スイツチS32,S25〜S31がそれ
ぞれ制御される。たゞし切替スイツチS25〜S32
対する制御は出力制御部22からの対応する制御
信号との論理積の出力で行われ、高レベルで出力
端子18側、低レベルで共通電位点側とされる。
As shown in FIG. 3A, when the load terminal 24 is
When a load command is given to each preset terminal P of flip-flops FF1 to FF8 , flip-flop FF1 is preset to "1" and the others are preset to "0", and this data pattern "100...0" is applied to the third
Shifted every clock at terminal 23 shown in Figure B,
The Q outputs Q 1 -Q 8 of flip-flops FF 1 -FF 8 change as shown in FIGS. 3C-J, respectively. The period of this clock is T, and the flip-flop
The outputs of each Q output Q1 to Q8 of FF1 to FF4 are connected to the power supply switches S1 to S8 , S23 , S24 , S17 to S17 in FIG.
S22 is controlled, and the disconnection switch in FIG .
S 16 , S 9 to S 15 and changeover switches S 32 and S 25 to S 31 are controlled, respectively. Control of the changeover switches S 25 to S 32 is performed by outputting an AND with the corresponding control signal from the output control section 22, and a high level is set to the output terminal 18 side, and a low level is set to the common potential point side. Ru.

出力制御部22も定制御部21と同様にD形フ
リツプフロツプFF9〜FF16の縦続接続により循環
形シフトレジスタが構成され、端子23のクロツ
クによりシフト動作が行われて定制御部21と同
期がとられる。端子24からのロード指令はフリ
ツプフロツプFF9〜FF16のプリセツト端子Pにも
与えられ、このロード指令によりレジスタ25の
各ビツト15〜15にそれぞれ格納されてい
る入力デジタル値の各ビツトデータ、例えば
“10100000”がフリツプフロツプFF9〜FF16にプ
リセツトされる。フリツプフロツプFF9〜FF16
各Q出力(第3図K〜R)と定制御部21よりの
切替スイツチS25〜S32を制御すべき出力とがAND
回路1〜1でそれぞれ論理積がとられて切替
スイツチS25〜S32がそれぞれ制御される。
Similarly to the constant control section 21, the output control section 22 also constitutes a circular shift register by cascading D-type flip-flops FF9 to FF16 , and a shift operation is performed by the clock at the terminal 23 to synchronize with the constant control section 21. Be taken. The load command from the terminal 24 is also given to the preset terminals P of the flip-flops FF 9 to FF 16 , and this load command causes each bit data of the input digital value stored in each bit 15 1 to 15 8 of the register 25 to be read. For example, "10100000" is preset to flip-flops FF9 to FF16 . Each Q output of the flip-flops FF 9 to FF 16 (K to R in FIG. 3) and the output to control the changeover switches S 25 to S 32 from the constant control section 21 are ANDed.
The circuits 11 to 18 perform logical AND operations to control the switches S25 to S32 , respectively.

以上のようにしてリング状に接続されたラダネ
ツトワークが切離スイツチにより1個所切離さ
れ、その時の電流モードラダネツトワークDA変
換器が構成され、そのアナログ出力が出力され、
オフとなる切離スイツチが順次移動するため、こ
れに伴つてラダネツトワークも順次1セクシヨン
ずつ回転する。よつて各セクシヨンから得られる
重み電流も順次切替えれらる。出力端子18の出
力を平滑回路26で平均化することにより、各セ
クシヨン間のバラツキが平均化される。各セクシ
ヨンは直列抵抗器11と、シヤント抵抗器12と
よりなり、これら相互間のバラツキも存在するた
め、ラダネツトワーク中の全抵抗器中の1つを可
変にしておき、シヤント抵抗11と12の比が
1:2となるように回転動作中に調整すれば、他
の多くの抵抗器11,12の抵抗値を高精度に調
整する必要はない。抵抗器11,12にバラツキ
が存在すると云つてももともと僅かであるため、
平滑回路26は1個のコンデンサと1個の抵抗器
とよりなる頗る簡単なものでよい。このように抵
抗器11,12としては高精度のものを必要とし
ないため、半導体集積回路内に抵抗器11,12
を組込むことができ、DA変換器を半導体集積回
路として構成することができる。切離スイツチ、
給電スイツチ、切替スイツチなどは電界効果トラ
ンジスタよりなるアナログスイツチを用いること
ができる。
The RADAN network connected in a ring shape as described above is disconnected at one point by a disconnection switch, a current mode RADAN network DA converter is configured, and its analog output is output.
Since the disconnection switches that are turned off are sequentially moved, the ladder network is also sequentially rotated one section at a time. Therefore, the weight currents obtained from each section can also be sequentially switched. By averaging the output of the output terminal 18 by the smoothing circuit 26, variations between the sections are averaged. Each section consists of a series resistor 11 and a shunt resistor 12, and since there are variations between them, one of all the resistors in the ladder network is made variable, and the shunt resistors 11 and 12 are made variable. If the ratio is adjusted during rotation so that the ratio is 1:2, there is no need to adjust the resistance values of many other resistors 11 and 12 with high precision. Even if there is variation in the resistors 11 and 12, it is small to begin with, so
The smoothing circuit 26 may be extremely simple, consisting of one capacitor and one resistor. In this way, the resistors 11 and 12 do not need to be of high precision, so the resistors 11 and 12 are installed in the semiconductor integrated circuit.
can be incorporated, and the DA converter can be configured as a semiconductor integrated circuit. disconnection switch,
As the power supply switch, changeover switch, etc., analog switches made of field effect transistors can be used.

〔第2実施例〕 第2図に示した例においては、切離スイツチS9
〜S16その他のスイツチのオン抵抗により各重み
電流が影響される。この影響をなくすためには、
従来技術の手法を用い、例えば第5図に第2図と
対応する部分に同一符号を付けて示すように、各
シヤント抵抗器12の切離スイツチと反対側にト
ランジスタTr1〜Tr8の一つのエミツタをそれぞ
れ接続し、そのトランジスタのコレクタを切替ス
イツチS25〜S32の各可動接点にそれぞれ接続す
る。トランジスタTr1〜Tr3の各ベースに電源2
7から一定電圧が与えられる。従つてトランジス
タTr1〜Tr2にはそれぞれその時のそのエミツタ
側に接続された抵抗器の接続状態に応じた重みの
定電流が流れる。例えば第5図では給電スイツチ
S1がオン、切替スイツチS32が共通電位点に接続
され、切離スイツチS16がオフの状態ではトラン
ジスタTr1に流れる定電流に対し、トランジスタ
Tr2〜Tr3には順次2分の1の電流が流れる。ま
たこの図は入力デジタル値が0100000の場合で切
替スイツチS26が出力端子18側、切替スイツチ
S25,S27〜S32が共通電位点側にされる。
[Second Embodiment] In the example shown in FIG .
~S 16 Each weight current is affected by the on-resistance of other switches. To eliminate this effect,
Using the prior art method, one of the transistors Tr 1 to Tr 8 is connected to the opposite side of the disconnection switch of each shunt resistor 12, as shown in FIG. The collectors of the transistors are connected to the movable contacts of the changeover switches S25 to S32 , respectively. Power supply 2 to each base of transistors Tr 1 to Tr 3
A constant voltage is applied from 7. Therefore, a constant current flows through each of the transistors Tr 1 to Tr 2 with a weight depending on the connection state of the resistor connected to the emitter side at that time. For example, in Figure 5, the power supply switch
When S 1 is on, changeover switch S 32 is connected to the common potential point, and isolation switch S 16 is off, the constant current flowing through transistor Tr 1 is
A half current flows through Tr 2 to Tr 3 in sequence. Also, this figure shows when the input digital value is 0100000, the selector switch S26 is on the output terminal 18 side, and the selector switch S26 is on the output terminal 18 side.
S 25 , S 27 to S 32 are placed on the common potential point side.

〔第3実施例〕 第2図は電流モードのラダネツトワーク形DA
変換器にこの発明を適用したが電圧モードラダネ
ツトワーク形DA変換器にもこの発明を適用でき
る。その例を第6図に第2図と対応する部分に同
一符号を付けて示す。この場合は各出力スイツチ
S33〜S40が抵抗器11,12の各接続点と共通の
出力端子18との間にそれぞれ接続される。また
各シヤフト抵抗器12の抵抗器11と反対側の端
がそれぞれ切替スイツチS25〜S32の可動接点に接
続され、これら切替スイツチS23〜S32はそれぞれ
共通電位点と定電圧源28とに切替え接続され
る。1つの切離スイツチ例えばS9がオフの状態で
その一方の側の出力スイツチS33がオン、他方の
側の切替スイツチS32が共通電位点に接続され、
更にその時のラダネツトワークの初段L7の短絡
スイツチS23が同時にオンにされ、これら切離ス
イツチS9〜S16、出力スイツチS33〜S40、切替ス
イツチS25〜S32、短絡スイツチS17〜S24は定制御
部21により制御され、切替スイツチS25〜S32
入力デジタル値の対応ビツトに応じて出力制御部
22により制御され、入力ビツトが“1”の時に
対応する切替スイツチを電源28側に接続する。
出力端子18に接続されたセクシヨンが入力デジ
タル値の最上位ビツトに対応させられる。第6図
の例では“1010000”を入力した場合であり、切
離スイツチS9がオフの状態において切替スイツチ
S25,S27が電源28に接続される。
[Third Embodiment] Figure 2 shows a current mode ladder network type DA.
Although the present invention is applied to a converter, it can also be applied to a voltage mode ladder network type DA converter. An example of this is shown in FIG. 6, in which parts corresponding to those in FIG. 2 are given the same reference numerals. In this case, each output switch
S 33 to S 40 are connected between each connection point of the resistors 11 and 12 and the common output terminal 18, respectively. Further, the end of each shaft resistor 12 opposite to the resistor 11 is connected to a movable contact of a changeover switch S25 to S32 , and these changeover switches S23 to S32 are connected to a common potential point and a constant voltage source 28, respectively. It is switched and connected to. When one disconnection switch, e.g. S 9 , is off, the output switch S 33 on one side thereof is on, the changeover switch S 32 on the other side is connected to a common potential point,
Furthermore, the shorting switch S23 of the first stage L7 of the Rada network at that time is turned on at the same time, and these disconnection switches S9 to S16 , output switches S33 to S40 , changeover switches S25 to S32 , and shorting switch S 17 to S24 are controlled by the constant control section 21, and the changeover switches S25 to S32 are controlled by the output control section 22 according to the corresponding bit of the input digital value, and when the input bit is "1", the corresponding changeover switch is Connect to the power supply 28 side.
The section connected to output terminal 18 is made to correspond to the most significant bit of the input digital value. In the example shown in Figure 6, "1010000" is input, and when the disconnection switch S9 is off, the changeover switch is
S 25 and S 27 are connected to power supply 28 .

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のDA変換器を示す回路図、第2
図はこの発明を電流モード形DA変換器に適用し
た例を示す回路図、第3図は第2図中の各スイツ
チに対する制御信号の一例を示すタイムチヤー
ト、第4図はスイツチ制御部の一例を示す回路
図、第5図はこの発明の他の例を示す回路図、第
6図はこの発明を電圧モード形DA変換器に適用
した例を示す回路図である。 11:抵抗値Rの抵抗器、12:抵抗値2Rの
抵抗器、14:定電流源、18:出力端子、2
1:定制御部、22:出力制御部、26:平滑回
路。
Figure 1 is a circuit diagram showing a conventional DA converter, Figure 2 is a circuit diagram showing a conventional DA converter.
The figure is a circuit diagram showing an example of applying the present invention to a current mode DA converter, Figure 3 is a time chart showing an example of control signals for each switch in Figure 2, and Figure 4 is an example of a switch control section. 5 is a circuit diagram showing another example of the present invention, and FIG. 6 is a circuit diagram showing an example in which the present invention is applied to a voltage mode type DA converter. 11: Resistor with resistance value R, 12: Resistor with resistance value 2R, 14: Constant current source, 18: Output terminal, 2
1: constant control section, 22: output control section, 26: smoothing circuit.

Claims (1)

【特許請求の範囲】 1 切離スイツチと、第1抵抗素子及び短絡スイ
ツチの並列接続との直列回路と、その直列回路の
一端に一端が接続され、上記第1抵抗素子の2倍
の抵抗値をもつ第2抵抗素子とよりセクシヨンが
構成され、このセクシヨンのN段(Nは3以上の
整数)がリング状に接続され、これら各セクシヨ
ンの接続点はそれぞれ各別の給電スイツチを通じ
て電源の一端に接続され、上記各セクシヨンの各
第2抵抗素子の他端にそれぞれ切替スイツチの可
動接点が接続され、これら各切替スイツチの一方
の固定接点は共通の出力端子に接続され、他方の
固定接点は上記電源の他端に接続され、上記セク
シヨンの一つにおける切離スイツチをオフとし、
そのオフとされた切離スイツチの一端側に接続さ
れた給電スイツチをオンとし、他端側に接続され
た切替スイツチを電源側に接続し、上記オフとさ
れた切離スイツチの上記他端側の隣接セクシヨン
の短絡スイツチをオンとし、入力デジタル値の各
対応ビツトに応じて上記切替スイツチをそれぞれ
電源側又は出力側に接続し、これらスイツチの設
定状態を、上記セクシヨンリング上での相対位置
を保持するように上記各切離スイツチについて順
次一定周期でオフとすることを繰返すスイツチ制
御部が設けられているDA変換器。 2 切離スイツチと、第1抵抗素子及び短絡スイ
ツチの並列接続との直列回路と、その直列回路の
一端に一端が接続され、上記抵抗素子の2倍の抵
抗値をもつ第2抵抗素子とよりセクシヨンが構成
され、このセクシヨンのN段(Nは3以上の整
数)がリング状に接続され、これら各セクシヨン
の接続点はそれぞれ各別の出力スイツチを通じて
共通の出力端予に接続され、上記各セクシヨンの
各第2抵抗素子の他端にそれぞれ切替スイツチの
可動接点が接続され、これら各切替スイツチの一
方の固定接点は共通の電源の一端に接続され、他
方の固定接点は上記電源の他端に接続され、上記
セクシヨンの一つにおける切離スイツチをオフと
し、そのオフとされた切離スイツチの一端側に接
続された出力スイツチをオンにし、他端側に接続
された切替スイツチを電源の他端側に接続し、上
記オフとされた切離スイツチの上記一端側と隣接
するセクシヨンの短絡スイツチをオンとし、入力
デジタル値の各対応ビツトに応じて上記切替スイ
ツチをそれぞれ電源の一端又は他端に接続し、こ
れらスイツチの設定状態を、上記セクシヨンリン
グ上での相対位置を保持するように上記各切離ス
イツチについて順次一定周期でオフとすることを
繰返すスイツチ制御部が設けられているDA変換
器。
[Scope of Claims] 1. A series circuit of a disconnection switch, a first resistance element, and a shorting switch connected in parallel, one end of which is connected to one end of the series circuit, and a resistance value twice that of the first resistance element. N stages (N is an integer of 3 or more) of this section are connected in a ring shape, and the connection point of each section is connected to one end of the power supply through a separate power supply switch. A movable contact of a changeover switch is connected to the other end of each second resistance element of each section, one fixed contact of each of these changeover switches is connected to a common output terminal, and the other fixed contact is connected to a common output terminal. turning off a disconnect switch in one of the sections connected to the other end of the power supply;
The power supply switch connected to one end of the disconnection switch that was turned off is turned on, the changeover switch connected to the other end is connected to the power supply side, and the other end of the disconnection switch that is turned off is turned on. Turn on the short circuit switch of the adjacent section, connect the above changeover switch to the power supply side or the output side according to each corresponding bit of the input digital value, and change the setting state of these switches to the relative position on the above section ring. A DA converter is provided with a switch control section that repeatedly turns off each of the above-mentioned disconnection switches at a constant period so as to maintain the disconnection switch. 2. A series circuit of a disconnection switch, a first resistance element and a shorting switch connected in parallel, and a second resistance element having one end connected to one end of the series circuit and having a resistance value twice that of the resistance element. A section is constructed, and N stages (N is an integer of 3 or more) of this section are connected in a ring shape, and the connection points of each section are connected to a common output terminal through separate output switches, respectively. A movable contact of a changeover switch is connected to the other end of each second resistance element of the section, one fixed contact of each of these changeover switches is connected to one end of a common power supply, and the other fixed contact is connected to the other end of the power supply. Turn off the disconnect switch connected to one of the sections, turn on the output switch connected to one end of the disconnect switch that was turned off, and turn on the output switch connected to the other end of the disconnect switch. Turn on the short-circuit switch of the section adjacent to the one end side of the disconnection switch that was turned off, and switch the changeover switch to one end or the other end of the power supply, depending on each corresponding bit of the input digital value. A switch control section is provided which is connected to the end of the disconnection switch and repeatedly turns off the disconnection switches at regular intervals so as to maintain the relative positions of the switches on the section ring. DA converter.
JP8079582A 1982-05-12 1982-05-12 Da converter Granted JPS58196722A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8079582A JPS58196722A (en) 1982-05-12 1982-05-12 Da converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8079582A JPS58196722A (en) 1982-05-12 1982-05-12 Da converter

Publications (2)

Publication Number Publication Date
JPS58196722A JPS58196722A (en) 1983-11-16
JPS6217416B2 true JPS6217416B2 (en) 1987-04-17

Family

ID=13728387

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8079582A Granted JPS58196722A (en) 1982-05-12 1982-05-12 Da converter

Country Status (1)

Country Link
JP (1) JPS58196722A (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100815754B1 (en) * 2006-11-09 2008-03-20 삼성에스디아이 주식회사 Driving circuit and organic electro luminescence display therof

Also Published As

Publication number Publication date
JPS58196722A (en) 1983-11-16

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