JPS62168224A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To increase the number of connectable registers without increasing the number of address buses by sending data in time division via a data bus to select the register to store the data sent next according to the combination of data and sending the data to the register for storage. CONSTITUTION:An upper decoder 5 selects an high-order register 8 by the value of an high-order address bus 3 and the data on a data bus 2 is put into the register 8. An intermediate decoder 7 selects an intermediate register 9 by the address value of the next address period and puts the 2nd data into the register 9. These data values are sent to the low-order decoders 13 and 14. A key decoder 6 is selected in the next address period and the contents of the register 8 are decoded and matched with the values of both decoders 13 and 14 for selection of a low-order register 10 or 11. Then the data on the bus 2 is stored in the selected low-order register.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit that allows effective use of an address bus.

[Summary of the invention]

The present invention provides a semiconductor integrated circuit which includes an address bus and a data bus and transmits and receives necessary data through these buses, in which a separately provided address bus is controlled according to the content of data sent to the data bus. The device is equipped with a hierarchically structured address bus, which allows a large number of elements to be connected to the address bus without increasing the chip size.

[Conventional technology]

Conventionally, there has been a data transmission system in which an address bus and a data bus are provided in i, and only the element specified by the address information sent to the address bus launches the data sent to the data bus at that time. Widely used. An L-chip microprocessor is an example of a semiconductor integrated circuit having such a data transmission system.

[Problem that the invention seeks to solve]

However, according to the conventional system described above, the number N of elements that can be connected to the address bus and the bit width n of the address bus
There exists a relationship of N<21. Therefore, in order to increase N, the bit width n must be increased.
A small-sized semiconductor device such as the above has the disadvantage that an address bus with a large bit width must be routed on the chip, and the chip size must be increased.

Furthermore, as the bit width n increases, the size of the decoder for decoding address information also increases, which poses a problem in that there is a limit to miniaturization of the chip size.

It is therefore an object of the present invention to provide a compact, high-performance semiconductor integrated circuit in which a large number of elements can be selected by an address bus without significantly increasing the area on the chip occupied by the address bus. There is a particular thing.

[Means for solving problems]

The configuration of the present invention for solving the above problems includes a data bus, an upper address bus, at least one upper decoder that decodes address information sent to the upper address bus, and a an intermediate decoder for decoding address information on the upper address bus; and an output of the intermediate decoder. an intermediate register provided corresponding to the intermediate decoder to take in the data on the data bus in response to the above, a lower address bus for transmitting the output of the intermediate register as address data, and a lower address bus of the lower address bus. at least one lower decoder connected to the lower address bus for decoding address data; a key decoder for decoding data on the upper address bus; and comparing the output of the lower decoder and the output of the key decoder. The device is characterized in that it includes a lower register provided corresponding to the lower decoder to take in data on the data bus according to the result.

[Effect]

The upper decoder and the upper register combined with the upper decoder perform the same operation as in the conventional art of sending required data into the register designated by the upper address bus via the data bus.

Data transmission to lower registers is performed using the lower address bus as follows. First, an intermediate decoder and an intermediate register are used to select an intermediate decoder using an upper address bus, and at this time, address data to be sent to a lower address bus is taken into the intermediate register via a data bus.

Therefore, at this time, one of the lower decoders responds in response to the address data sent to the lower address bus. The lower register provided corresponding to the lower decoder that responded takes in the data on the data bus at that time when the key decoder becomes valid in response to the contents of the upper address bus at that time.

〔Example〕

FIG. 1 shows an embodiment of a semiconductor integrated circuit according to the present invention. The semiconductor integrated circuit 1 has a control unit 4 connected to a data bus 2 and a higher-order address bus 3, and outputs desired data D according to address data A sent from the control unit 4 to the higher-order address bus 3. This is a circuit for sending data to the register.

An upper decoder 5, a key decoder 6, and an intermediate decoder 7 are connected to the upper address bus 3, and an upper register 8, an intermediate register 9, and a lower register 10.11 are connected to the data bus 2. ing.

The upper decoder 5 and the upper register 8 form a pair, and when the upper decoder 5 is enabled by the address data sent to the upper address bus 3, the upper register 8 is activated by the signal S1 output from the upper decoder 5. It has a conventional configuration in which data being sent to the data bus 2 is stored.

In the above, only one set of upper decoder and upper register is shown, but as many wls as desired may be provided.

The intermediate decoder 7 and the intermediate register 9 are
1 to the lower address bus 12 provided on the output side of the . It is provided to send desired lower address data from the control unit via the data bus 2. Address data to be sent to the lower address bus 12 is sent to the data bus 2 in the control unit 4, and predetermined address data for enabling the intermediate decoder 7 is sent to the upper address bus 3 at this time. As a result, the intermediate decoder 7 outputs a signal S2 indicating that the intermediate decoder 7 is enabled, and the data to be sent to the lower address bus 12 is taken into the intermediate register 9 via the data bus 2, and the lower address The signal is sent to bus 12.

The lower address bus 12 includes a plurality of lower decoders 13,
14 are connected, and any one lower decoder corresponding to the address data sent to the lower address bus 12, for example lower decoder 13, is enabled. The output of each lower decoder is connected to an AND gate 16, one input terminal of which is connected to the output line 15 of the key decoder 6.
17, and the outputs Ss and S4 from these AND gates 16 and 17 are supplied to the lower register 10.11 as a signal for operating the corresponding lower register 10.11. ing.

Therefore, when the control unit 4 sends the predetermined address data for the key decoder 6 and the data to be stored in the lower register I3 to the address bus 3 and the data bus 2, respectively, the key Since the level of the output line 15 of the decoder 6 becomes rHJ and the output level of the AND gate 16 becomes rHJ, at this time the data bus 2
The desired data sent to the lower register 1o is stored in the lower register 1o.

As can be seen from the above explanation, when it is desired to store data in one lower register, the intermediate decoder 7 and the intermediate register 9 are used to send address data to enable the lower decoder 14 to the lower address bus I2 in advance. After that, the address data that activates the key decoder 6 is sent to the upper address bus, and at the same time, desired data is sent to the data bus 2.

As can be seen from the above explanation, the address information of the lower decoder selected by the lower address bus 12 is sent out via the data bus 2, so even if the number of lower decoders increases, it is necessary to increase the bit width of the upper address bus 3. Therefore, the number of decoders that can be specified by the upper address bus 3 can be increased apparently without increasing the capacity of the upper address bus 3. Therefore, it is unnecessary to increase the chip area for the address bus. This makes it possible to keep the chip area small.

Note that since the lower address bus is local,
Unlike the upper address bus, there is no need to route it throughout the chip, and even if a lower address bus is added, the resulting increase in chip area will hardly be a problem.

〔Effect of the invention〕

According to the present invention, since the address bus has a double structure as described above, it is possible to increase the number of elements that can be connected to the address bus without increasing the chip area. An integrated circuit can be realized.

[Brief explanation of drawings]

The drawing is a circuit diagram showing an embodiment of a semiconductor integrated circuit according to the present invention. 1...Semiconductor integrated circuit 2--Data bus 3--Upper address bus 4...Control knee unit 5--Upper decoder 6--Key decoder 7...Intermediate decoder 8-Upper register 9...・Intermediate register 10.11...-lower register 12--lower address bus 13.14...-lower decoder and above

Claims (1)

[Claims] a data bus, an upper address bus, at least one upper decoder for decoding address information sent to the upper address bus, and corresponding to the upper decoder for fetching data from the data bus in accordance with the output of the upper decoder. In a semiconductor integrated circuit comprising an upper register provided as an upper register, an intermediate decoder for decoding address information on the upper address bus, and an intermediate decoder for taking in data on the data bus in response to an output of the intermediate decoder. an intermediate register provided corresponding to the decoder, a lower address bus for transmitting the output of the intermediate register as address data, and at least one connected to the lower address bus for decoding the address data of the lower address bus. one lower decoder, a key decoder for decoding data on the upper address bus, and a key decoder for comparing the output of the lower decoder with the output of the key decoder and fetching the data on the data bus according to the result. A semiconductor integrated circuit comprising a lower register provided corresponding to a lower decoder.