JPS62154983A - Video memory - Google Patents

Abstract

PURPOSE:To obtain a 1H (one horizontal scanning period) and a 2H delay signal without increasing the number of pins of an IC memory by outputting two video data which are delayed by different horizontal scanning lines behind input video data to an output terminal alternately at a frequency 2f. CONSTITUTION:For example, a write address is designated at the same frequency with the input data and one bit A0 of it alternates between '0' and '1' every time 1H data is written, so that the input data inputted at some sampling rate is written successively on a memory cell array 107 having, for example, 2H capacity. A read address have an address A0 alternating between '0' and '1' at a rate twice as large as the sampling rate. Therefore, writing operation is performed for two storage areas which are divided by the address A0 alternately at intervals of, for example, 1H and reading operation is performed for the two storage areas alternately in clock units. Consequently, video data which are delayed by two different delay quantities are obtained at the same time without increasing the number of pins of the IC.

Description

[Detailed description of the invention]

[Industrial Application Field] The present invention relates to an image-dedicated memory suitable for image signal processing. [Prior Art] In digital video equipment, line memory (a line indicates one scanning line) is an important memory used in image signal processing circuits such as comb filters, vertical spatial filters, or interpolators. It is one of the most popular devices. An example of an image signal processing circuit using line memory is given in the atrium J: 1979 Journal of the Television Society, Vol. 33, No. 4.
No., PP 271--276 entitled "Synthesis and Separation of Color Television Signals". There are two-dimensional filters for Y/C separation circuits in digital television. As discussed in this document, two-dimensional filters for Y/C separation can be used to separate the current video signal and
((H indicates 1 horizontal scanning period.) Compared to the I FI type that performs calculations using the previous video signal, the current video signal and this] TIj'; and the 2TI previous video signal and The 2H type, which performs calculations using
There is K5808P. This memory has an IK x 8 bit I~ configuration, and a 10-bit AT1NO is connected to J from the outside.
I can get it. NTSC system Te1 Novi signal at 4 fs
When sampling at the frequency c (fsc is the frequency of the color subcarrier), the number of samples within 11■ is 910, so one memory IC can handle a video signal quantized to 8 bits 1~. It has a capacity of I II. Therefore, with a circuit configuration using these two memories and an address counter that counts 1.7-7 minutes (910 dots to 1), an IH delay signal and a 2 I-I delay signal can be obtained. [Problem to be Solved by the Invention 1] In order to obtain the LTI delay signal 2HilY' extension for the current video signal using the conventional IC memory described in 1-1, two ICs are required. To generate an address, for example, the address counter to IO pin 1 is the number of cores, and the number of times: l'8 configuration is decoding (and the memory peripheral circuit rule (Q increases -4-). The object of the present invention is to use one T, C memory and a large number of peripheral circuits to convert, for example, +, I1.+ and 2+'l delay I1-? to IC memory. The goal is to create a video memory that can be obtained without increasing the number of bins. [Step T for solving the problem] In order to achieve the purpose of , 11 (at least 2 H)
It has a built-in AT 1 counter. Among these address counters, the address counters are as follows:
For example, 3 for the number of samples in 2f-I with a clock having the same frequency as the data sampling frequency. The counting counter and read address counter are clocked at twice the frequency of the write address counter (for example, 2H).
A counter is used to count X2 dots (number of samples in the memory), and the address of the most significant bit of the output of the write address counter and the address of the least significant bit of the output of the read address counter are made to correspond on the memory cell array. As a result, the data before IH and the data before 2H are alternately read from the memory cells corresponding to 2H in units of tarlocks of the read address counter. [Function] In the above technical means, for example, the write address is
Specified with the same frequency as the input data. Of these, 0.1 is repeated every time 1-bit (hereinafter referred to as A) writes 111 minutes of data. Input data input at a certain sampling array 1 to 1 is sequentially written into a memory cell array having a capacity of, for example, 2H. The read address is an address at a rate twice the above sampling rate, 4. Afl switches to 0.1. Therefore, the pumping operation is at address A. For example, read operations are performed alternately in two storage areas divided by lIT, and read operations are performed alternately in clock units between these two storage areas. By doing this, it is possible to alternately read, for example, video data 1-H before and 2-I before video data inputted from the input terminal to the double ray 1. Ko'I

[by. It is possible to simultaneously illuminate video data with 2-, ) different delay amounts without increasing the number of IC pins,
The signal processing circuit becomes bloody. [Example] Hereinafter, an example of the present invention will be described using FIG. 1. 1st
In the figure, 100 is an image memory according to the present invention, 101 is a video input terminal, 1. C) 2 is a video output terminal, 103
is the clock signal (shoulder, r (input terminal, 104 beam cell 1
-Signal RE S input terminal, 105 is power supply terminal, 106
is the ground terminal r・, L O7 is the memory cell array, 1.08
is the write 1 to atto 1 nos decoder, 109 is the read address decoder, 1-io, 112, 114 and 119
is a binary counter, and 111 and 113 are 910-decimal counters. 1 ], 5 are switching circuits, 116 is a delay circuit, and 117° and 118 are latch circuits. Further, FIG. 2 shows timing charts 1 to 1 for explaining the operation of the embodiment of FIG. 1. In this embodiment, the NTSC video signal is, for example, 4 fs.
The case of sampling at a frequency c will be explained. In this case, the number of samples within one horizontal scanning line is 91.0. The operation of this embodiment will be explained below. It is assumed that the memory cell array 107 has a capacity of 2H. Further, it is assumed that each memory cell has data lines for writing and reading, as shown in FIG. 7, for example, so that writing and reading of data can be performed independently. It is also assumed that the counter and latch circuit used in this embodiment operate at the falling edge of the clock signal. From the clock signal input terminal 103, 8.
A clock with a frequency fsc (hereinafter referred to as 8 f scCL
Marked as K. ). This signal 8 f sec L K is shown at 2 a in FIG. This signal is led to a binary counter IJ4 jar and frequency-divided to create a clock with a frequency of 4·1°SC (hereinafter referred to as 4fsCC'L, K without note 3).
get. The output signals 2cl and 1' of the counter 1-19 and the output signal 2f1 of the counter 1-1-4 are respectively;
5. Not shown in 2c and 2f1 in FIG. counter 11
2゜113.1.14 is a synchronous counter, and the end r.
The reset 1-signal RES inputted from 104 is reset. Therefore, 8'sc CT-, 4 f scC for the K signal: The phase of the T, K signal 2f1 is determined by the reset signal RES, 11.
, this reset signal RES is shown at 2g in FIG. By inputting this reset signal RES from the outside, the read address +jE and write 1- address can be initialized. Also, the counter [10, 111,, 1
19 is also a synchronous counter, and the reset 1-signal RE S
Reset by the signal RES' delayed by the delay circuit 11G. The delay circuit 116 will be described later in this embodiment. Then, the delay amount at delay circuit]-16 is set to 2 at 8fscCLK.
Clock minutes. This second reset signal RES' is shown at 2b in FIG. The video input signal DI is input to the input terminal 101 at the timing shown in FIG. 2F. This input signal DI is guided to the latch circuit 117, latched with 4fsc (?: LK signal 2C, and then written to the memory cell array 107. The two counters 110 and 11] constitute a write address counter that generates a write address. Counter 111
is the 4fscCLK signal 2c from the output of the counter 119
This is a 910-decimal ring counter that counts the output of this counter 111 as 10 bits WA, -WA, of the 11 bits of the write address. and leads to the write address decoder 108. This 10-bit address WA1~
W A s. is expressed in decimal notation as 28 in FIG. The counter 110 is a binary counter, and every time the counter 111 counts 910, that is, every IH, 0.
Repeat step 1. This Karan, 8. The output of R1]0 is sent to the remaining 1. bit WA, and is led to the write 1 hair address decoder 108. This lie I-address WAo is shown at 2d in FIG. Rai I - address decoder 108 is Rai I
-Decode addresses WΔ11 to WA1o and set each memory cell in the memory cell array 107 corresponding to I?
1, and 11: Set it to a state where it can be loaded. For the sake of explanation, the memory cell array 107 is divided into 82 areas A and 82, and when the address WΔ,1 is O, the memory cells in the A area are accessed, and when WΔ,l is 1, the memory cells in the B area are accessed. If so, the video input signal I〕■
are continuously written in the area A of the memory cell array 107 for 1.1-r, and the data for the next IH is continuously written rIF into the area B of the memory cell array 107. From then on, this operation is repeated at a 2H cycle. 2f in FIG.
This shows that data is sequentially written to memory cell No. 9, and then from memory cell No. 0 to memory cell No. 909 in the 2B area. On the other hand, three counters 112, 113 . and ]14 constitute a read address counter that generates a read address. The counter 113 is a 910-decimal ring counter that counts the 4fscCLK signal 2h from the output of the counter 114.
Read 0 bits from address 11 bits WA, ~W
A engineer. 10-bit addresses RA1 to RA corresponding to
This leads to the read address decoder, 09. These 10-bit addresses RA□ to RA1. ．． is expressed in decimal notation as 2k in FIG. The counter 112 is 2
It is a decimal counter and repeats 0.1 every time the counter 113 counts 910, that is, every 1H. This counter 1
The output signal 2f of No. 12 is shown at 2f in FIG. The output signal 2h of the counter 114 and the 1 inverted output signal 2h are led to the switching circuit 115, and these two signals are sent to the counter 112.
It is controlled and switched by the output signal 2f of 0 and 1. The output of this off (gate circuit 1. + 5) is set to the write address W.
The read address RA corresponding to λ·1 is directed to the read at 1 node 1-der 109. Switching circuit 11
5, 1-9, and when signal 2f is O, signal 2h is
When signal 2j is 1, signal 2h is selected
), set the read address RΔ11 in this case to the second
It is shown at 25 in the figure. In this way, the output signal 2h of the binary counter 114 after the 1:reset is applied to the reset 1-signal Rl>S.
? Δ1°, and then 1. Same counter for TI period! The inverted output signal 2h of No. 14 is RA. By switching like this, j;lro1. In the 11th period,
First, data is read from the memory cell in area A, and then data is read to area B, area... Which intersection Jl'? In contrast to (line -), in the 9th 1 f-I period, first ryo 1 bite 1
After reading data from memory cell No. 3, reading is performed alternately from area 1 or Δ and area B. Below, this operation will be described as 2 I-
Repeat in one cycle. Read address IkuΔ1. ~． 11
. The signal read from the memory cell specified by the read address decoder] 09 by RA, o is led to the latch circuit 118, latched at 8fscCLK, and then output to the video output terminal 1.
Output to 02. This output signal D○ is shown at 2f in FIG. The signal Do output in this way is the input signal D
For I, the signals before IH and before 2H are alternately arranged. Here, when writing data to the memory cells in the area A (or B) of the memory cell array 107, the data read from the memory cells in the area A (or B) is delayed by 2H, and (or A)
The data read from the memory cells in the area is the IHH extension signal. For example, data A. When is entered,
Output data A. is 2H delay, output data B is IH
This is the H extension power. Similarly, data B. is input, the output data Bfl is a 2H delayed output, and the output data A is an IHH delayed output. As shown at 2]- in FIG. 2, the output terminal 102 has a 2H delay, 12, relative to the input signal DI. The extended output and the IHH extended output are output, but the 19th switching circuit 115 switches between the output 2f of the counter 114 and the inverted output 2h every III.
Therefore, the output order of the 2N delayed signal and the IHH delayed signal is constant i', I; for example, in this embodiment, the output order of the 2N delayed signal and the IHH delayed signal is i', I; The I-T delayed signals are output in order. 1 j'9, in this embodiment, the address counter is at a predetermined count? After going seven times, it automatically resets to 1, so IJ-1? Glue curing 1~ from the hot terminal 104 can be performed once after turning on the power supply R, or once every 2 hours. If this embodiment is used, video signal human input/1 IH
To obtain an H extended output and a 2f-T delayed output in the dark with a simple circuit configuration and control signal, and to reduce the circuit scale, for example, in a line filter, an intra-field scanning line interpolation circuit, etc. becomes possible. In the embodiment shown in FIG. 1, the input/output is 1 bit 1~, but the memory cell array 107, the input terminal 101, the output terminal 102, the latch 11, and the latch 11 have n connections 117 and 118 each, and an n-bit video signal is provided. It is also possible to use an n-bit configuration video memory that delays the . At this time, the CoH delay output and the 2H
Since the delayed output is output from the same output pin, 2H terminals are required for data input/output. Note that this also applies to other embodiments described below. If it is desired to take out the IH delayed output and the 2H delayed output separately, the circuit configuration shown in FIG. 3 may be used. In FIG. 3, 100 is the video memory according to the present invention shown in FIG. 1, 301 is a video signal input terminal, 302 is a reset signal input terminal, 303 is an input terminal for 8fscCT, 3
04 is the current signal output terminal, 305 and 306 are each IH
309 is a frequency dividing circuit, 31.0 and 311 are latch circuits, and 314 is an inverting circuit. In this way, the 180° phase obtained by dividing the 8fscCLK supplied to the video memory 100 by two
By latching the output signal of OO, the desired signal output can be set to 11.
) , , + , It is suitable for image processing such as line comb filters and scanning line interpolation circuits. For example, output end 1”
-2Ir of the current signal from 304 and the output terminal 306
The delayed signal is multiplied by -1/4, and the output terminal f30
The color signal component can be extracted from the NTSC signal by multiplying the ll-1 delay amount by 1/2 and adding these values. In the embodiment shown in FIG. 1, by changing the delay amount of delay circuit II (3), the timing of resetting the write 1-at 1 no counter can be adjusted. For example, in this example, the delay amount is exactly LH;
; and 2f+. Also, switching circuit L
15, 1; Reverse the switching timing of signal 2h and signal 2h, or set the negation of the output of switching circuit 115 as read address RAo. 17 So and 2. rT
15. The output order of the delay switch 3 can be changed. In the embodiment of FIG.
As shown in the timing chart of FIG. 2, a video signal exactly 1H and 2H before the video input signal is obtained as an output, and the falling edge of the 4fscCLK signal 2c, which is the clock signal of the latch circuit 117, is obtained as an output. The timing is 2H delay amount, and the timing of the rise of signal 2c is 1. An H delayed signal is output. This facilitates timing management when a plurality of video memories are connected in series. This will be explained using the circuit configuration shown in FIG. FIG. 4 shows IH, 2H, 3H and 4H delay amount outputs obtained by connecting two video memories according to the present invention in series. In Fig. 4. 100a and 100b are video memories according to the present invention shown in FIG.
H-delay output terminals 312 and 313 are latch circuits, and other parts that are the same as in FIG. 3 are denoted by the same reference numerals. Video memories 100a and 100b
To, 17°, 16. are supplied with the same sensor l- signal and the same clock signal. Since the IH delay output and the 2I (delay output) appear at the intersection 1j in the output of the video memory 100a, the phase difference obtained by dividing 8fscCLK by 2 is 180°, as in the case of the circuit shown in FIG. 4. By latching this output signal with the fsc clock, the IHH delayed output and 2[I delayed output are outputted to the output terminals 305 and 306, respectively. In addition, the output of the video memory 100a is guided to the input of the video memory i-00b, but at this time, the timing at which data is taken into the video memory 100b, that is, the 4E scCT in the video memory 1 (OOI)
At the falling edge of K, the video memory 100a
Since the 2I-1 delay amount signal is always outputted to the output of , only the 2H delay amount is input to the video memory +00b without particularly thinning out the data. Therefore, the output of the video memory 100b has 311 extensions and J
Since the A and 4H delay amounts appear alternately, this is also latched by the 4[sc clock, which has a phase difference of 180 degrees, and the 18
. By doing so, a 3H delayed output and a 4H delayed output are obtained at output terminals 307 and 308, respectively. This makes it suitable for image processing such as higher-performance line comb filters and scanning line interpolation circuits. In this embodiment, the input signal is an NTSC signal at 4 fsc.
However, the present invention is not limited to this, and in general, the capacity of the memory cell array is set to 2m.
By setting the pitch to 1 and making the counters 111 and 113 m-ary counters, it is possible to support other systems in which the number of samples in the IH period is m. In addition, although the operation has been explained by dividing the memory cell array 1.07 into two areas A and B, these are address areas, and the physical arrangement of memory cells in the memory cell array 107 is specified in a specific manner. It's not something you do. Delay circuit 116
When the delay amount in the 8fscCLK signal corresponds to an even number of clocks, the counter 114 and the counter 115 have the same operation and can be used in common. The switching circuit 15 is used to switch the output signal 2h of the counter II/I and the inverted output signal 2]1 by τ1νj according to the level of the output signal 2j of the counter 12. Function i: 1, (li 2f1 and signal 2f, or signal 2h
The real JSJ can also be obtained by taking the 11-alternative OR of the signal 2f and the signal 2f, or by its negation. FIG. 5 shows another embodiment of the video memory according to the present invention. The feature of this embodiment is that the number of dots in one scanning line period can be externally set to any number of dots by the period of the reset signal RES. A in Figure 5
9, 500 is a video memory according to the present invention, 50] is an output terminal for an 11T/2f1 delay discrimination clock signal, 50
2 is the decode signal output terminal, 50; 3 is the memory self 1 noise, 504, 506, 50''7, 50≦1
112 j (1: counter, 505, 508 are 1024
decimal 10-bit 1-counter, 510 is line 1 to address decoder, 51]-line 1-address decoder, 51X
3 is A, a decoding circuit, and 514 is a BI decoding circuit 2.
19. 515 is a decoding circuit, 516 to 524 are various gate circuits, and 525 is an edge detection circuit. Here, it is assumed that the memory cell array 503 has a capacity of 2048 bits, and each memory cell shown in FIG. 7 is used. Furthermore, when a set signal and a reset signal are input to counters 504 and 509 at the same time, set is given priority. The operation of the embodiment shown in FIG. 5 will be explained using the timing chart shown in FIG. 8fscCLK is input from the input terminal 103. This is shown in FIG. 668. Also, input terminal 1
From 04, the IH cycle reset pulse RES is input. This reset pulse RES is shown in FIG. 6b. The counter 507 divides the frequency of this reset pulse RES by 2.
Count H. The output signal 6g of this counter 507
is shown in FIG. 6, 6g. Counter 509 is normally 4fsc
CLK is output, but when the reset pulse RES is input from the input terminal 104, the reset and set are repeated every ]H. The output of this counter 509 is read address 1-pi+-RΔ9. 1. This area RAo is not shown in FIG. 66h. 1o pi1-counter 508 is counter 5
A signal 6j obtained by inverting the output signal of 09 every IH is counted. This signal 61 is shown in FIG. 661. Read the output of the counter from 10 bits 1 to the remaining 1 of the addresses
0 bit RA, ~RA,. The read door 1 leads to the decoder 5]-1. 10 bit counter output RA
□~RA, , expressed as an IO subnumber is shown in FIG. 6, 6j. This address [kuΔ. After the data read from the memory cell accessed by ~RAlo is latched by the latch circuit 118, the video output signal 1 output from the output terminal 102 is shown in FIG. 6K. The decode circuits 513 and 514 have read addresses RA, . . . ~R.
A1. is input, and the at I nos of the first memory cell 1-1 of the area 64 and the first memory cell of the area B are decoded and a pulse is generated. Is this l? , the pulse of counter 50
gated by the output signal of 7. The counter 504 is set every ]-H, and cell 1- is repeated. The output signal of this counter 504 is guided to the write address decoder 51-0 as a write address WAo. A counter 506 divides the frequency of 8fscCLK by two to obtain a 4fsc clock signal 6C. counter 50
5 is a 10-bit counter that counts the signal 6C, and its output is the write address WA, -WA,. and leads to write address decoder 510. counter 505,
506 are both reset to IH once. counter 5
The output signal 6C of 04 is shown in (3) in FIG. 6, and the output WA of the counter 505. ~W A , , , expressed in decimal notation is shown in Figure 6 (
5). Video signal 1 input from input terminal 101
(2) is shown in FIG. 6, 6f. After this video input signal DI is latched by the latch circuit 117, the write address WA
o-W A 1. is written to the memory cell specified by o. With the above operation, the video signals before IE and 2H before the video input signal DI are sent to the output terminal 102.
The q horn is output to the tb. In the embodiment of FIG. 5, by changing the decode value in the decode case 516.517, the lie 1 hair address counter y=4i* +
Since the timing of recell l-, j: and cell 1- of the counter that is The length of LI is determined by the period of externally applied pulse RIE S.The number of samples of Ill is 1024 at
Z1 can be applied to a system of less than 1 \, and it is also possible to set the amount of delay. 1, the counter 505 is 102.
After clicking 4, until it is reset, the video signal is 1).
11 For example, the resel 1 pulse signal RES can be manually input to a system with 1024 or more samples of i I-r. Even if I carve it into
l, de and 2f1 slow 2:3. You can get a delayed signal. At this time, since the video signal of 111 dots exceeding 1024 clocks is not written into the video memory, this period may be set as a blanking period of the video signal. Decode circuit 515 reads read address RA. ~RA1. is decoded and output to the output terminal 502. If the decoded value at this time is frequently used], and the number of samples of H is, for example, 91-O, then if the decoded output is used as the reset signal RES and the terminal 104 and the terminal 502 are connected, the reset signal can be input from the outside. There's no need to give it. Edge detection circuit 525 detects edges of reset signal RES. Therefore, since the input reset signal RES may have a long pulse width spanning several clocks, the horizontal synchronization signal can be used as it is as the reset signal RES. A signal 6j, which is an inverted version of the signal 6j, is output to the output terminal 501. As shown in Figure 6, belief 24. At the start of signal 61, the ITT delay signal is output as signal 6i.
A 2H delayed signal is output at the rising edge of . If the signal 6j or 6j is output to the A section and the signal 1' is changed to 1, the signal 6j or 6j is outputted to the outside. If you want to extract the H delay signal and the 20 delay signal separately, you can latch the video input signal;r-)0 with the signal from the output terminal 501 or the inverted signal3. Therefore, when this embodiment is used as shown in FIG. 3 and 'lI'2+, the Glock frequency divider circuit 309 is not required. In the embodiment of the present invention, the memory capacity -111, is set to 2f-
(and 1H and 2 I-T delay signals ti
), but the present invention is not limited thereto.
Instead, for example, the memory capacity -1il: is set to /1]■, and the I II delay and 4H delay output are set to 7,1, or the 2H delay and 4. I-I delay output to 1
This is characterized by outputting signals with different amounts of delay, such as signals j1 and ru, from the same terminal. FIG. 8 shows an example of the configuration of a 2T-T type Y/C/l>female comb filter using the embodiment of the video memory according to the present invention shown in FIG. In Figure 8, 500 is the fifth
An n-bit W video memory according to the present invention shown in the figure,
8.01 to 804 are latch circuits, 805 and 807 are adders, 806 is a multiplier, 808 is a subtracter, 809 is a video signal input terminal, 810 is a clock terminal, 811 is a color signal output terminal, 812 is a luminance A signal output terminal 813 is an inverting circuit. Latch circuit 802.803. and 8
04 output respectively 2H delay bone, IHH delay signal,
You can get the current signal. Therefore, a 27-T type comb filter can be realized with a simple circuit configuration as shown. [Effects of the Invention] According to the present invention, it is possible to easily obtain IH and 2H delay signal outputs for video signal input without increasing the number of pins of the IC memory, and thus the video memory is suitable for various image signal processing. can be realized.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the video memory according to the present invention, FIG. 2 is a timing chart for explaining the operation of the embodiment of FIG. 1, and FIGS. 1 is a block diagram showing an application example using the video memory of the embodiment shown in FIG. 5, FIG. 5 is a block diagram showing another embodiment of the video memory according to the present invention, and FIG. 6 is a block diagram showing the operation of the embodiment of FIG. 5. Timing chart to explain. FIG. 7 is a circuit diagram showing an embodiment of the memory cell used in the video memory according to the present invention, and FIG. 8 shows the configuration of a Y/C separation comb filter using the video memory of the embodiment shown in FIG. It is a block diagram. 100... Video memory, 107... Memory cell array, 108... Write address decoder. 109...Read address decoder, 110°11.
2,114,149...binary counter. 111, ii3...91. O advance counter No. 5 hanging VCc Question 8 ■/7 Out/J

Claims (1)

[Claims] a storage means capable of storing digitized n-bit video data for at least two horizontal scanning periods; n input terminals; n output terminals; means for writing into a storage area; means for guiding the n-bit video signal read from the storage area to the n output means; and a clock signal having a frequency f as a clock pulse for at least two horizontal scanning lines. and a read address counter that counts the number of samples for at least two horizontal scanning lines using a clock signal with a frequency of 2f as a clock pulse, and the most significant bit of the address output of the write address counter. and the least significant bit of the address output of the read address counter are configured to be the same address on the storage area, so that two videos delayed by different horizontal scanning lines with respect to the input video data are generated. A video memory characterized in that data is alternately output to the output terminal at a frequency of 2f.