JPS62147762A - Read-only memory - Google Patents

Abstract

PURPOSE:To prevent generation of unwanted breakdown of joint even for high packing density of memory cell by making deeper the P-N junction position of memory cell than the P-N junction position of transistors used in the peripheral circuit. CONSTITUTION:The base-emitter junction 23 can be formed at the position deeper than the base-emitter junction 8 by forming a base region 6 and an emitter region 7 of transistor which forms a peripheral circuit with the other process than that to form a base region 21 and an emitter region 22 of a memory cell. Thereby, resistance to thermal impact during the mounting and sealing process can be improved even when the occupation region of memory cell may be narrowed and missing of program due to unwanted breakdown of junction can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a read-only memory device, and more particularly to a programmable junction-destructive read-only memory device formed on a semiconductor substrate.

[Conventional technology]

A conventional junction-destructive read-only memory device consists of an array of memory cells and peripheral circuitry that supports the functionality of the array of memory cells, each of which is shown in FIG. As shown in FIG.
The pace area 101 formed in 2 and the pace area 10
1 and an emitter region 102 formed therein. Polycrystalline silicon 10 is provided in the emitter region 102.
:l The aluminum wiring 104 is electrically connected through n
The transistors that make up all the peripheral circuits in 5 have the same structure as the above memory cell, and each layer and region 91.92°101.102 etc. that make up the memory cell corresponds to the layers and regions of the transistor that makes up the peripheral circuit. Since they are formed simultaneously in the same process, the pace emitter junction depth is formed at the same position even if the size of the transistor is different.

In a junction destruction type read-only storage device having such a configuration, since the passing current is based on the presence or absence of destruction of the binary information t-pace emitter junction, when programming, it is necessary to A high voltage is applied between the pace emitter of a memory cell selected in advance, causing junction breakdown between the pace and emitter.

[Problem to be solved by the invention]

However, in conventional junction-destruction-type memory devices for continuous production, the memory cells and transistors constituting the peripheral circuits were formed simultaneously in one process, making it difficult to reduce design rules and improve the degree of integration. As time progresses, the junction position between the pace emitter becomes shallower, and when thermal shock is applied during mounting and encapsulation of the semiconductor substrate 90, even memory cells that have not caused junction breakdown between the pace emitter due to high voltage will be damaged. A problem arises in that junction breakdown as shown at 105 in Fig. 2 occurs, and the program assigned to each memory cell array is destroyed.In addition, junction breakdown occurs in places due to high voltage. In the memory cell, as shown in FIG. 3, the junction breakdown trace 106 reaches the collector-base junction? There was a problem of deterioration.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a read-only memory device that does not cause undesired junction breakdown even when memory cells are highly integrated.

[Means for solving problems]

Is the present invention a read-only storage device? If the PN junction position of the memory cell is deeper than the PN junction position of all peripheral circuit transistors, even if the area occupied by the memory cell is reduced, undesired PN The gist is to prevent joint failure from occurring.

〔Example〕

FIG. 1 is a cross-sectional view showing one embodiment of the present invention, in which a semiconductor substrate 1 is provided with a buried layer 2, an epitaxial layer 3.4 is grown on the buried layer 2, and these buried layers 3 and 4 are grown. The embedded layer 2 and the epitaxial layer 3.4 are separated gaseously by a field oxide film 5.

A pace region 6 is formed on the surface of the epitaxial layer 3. An emitter region 7 is formed on the surface of this space region 6, and a PN junction 8 between the pace and the emitter and a PN junction between the collector and the paste are formed. 9 is formed. Contact holes are appropriately formed in the silicon dioxide film grown on the surface of the semiconductor substrate 1, and the epitaxial layer 3 and the emitter region 7 are connected to each other through the contact holes through the polycrystalline silicon 10 and 11. A metal compound such as a platinum silicide film 12.13 and a high melting point metal such as TiW
Barrier metal layers 14.15 are stacked, and aluminum wiring 16.17 is connected to these barrier metal layers 14.15. - In the space region 6, a barrier metal layer 19 is laminated via a metal compound such as a platinum silicide film 18, and an aluminum wiring 20 is connected to the barrier metal layer 19. As a result, the wiring structure of the transistors constituting the peripheral circuit has barrier metal fi14.15.
1'lf and 1'lf, respectively, so short circuits due to aluminum spikes will not occur even if the transistor size is reduced and the junction is made shallower.

- 10,000, the memory cell has a space region 21 formed on the surface of the epitaxial layer 4 and an emitter region 22 formed on the surface of the space region 21, resulting in a space-emitter junction 23. is formed. An aluminum wiring 25 is connected to the emitter region 22 via polycrystalline silicon 24.
Also contributes to the prevention of aluminum spikes.

In a read-only storage device having such a structure, the pace region 6 and the emitter region 7 of the transistor constituting the peripheral circuit, the pace region 21 and the emitter region 22 of the T mesori cell.
By forming the base emitter junction in a process separate from that of the base emitter junction, it is possible to form the base emitter junction at a deep position.As a result, even if the area occupied by the memory cell is reduced, , resistance to thermal shock during mounting and encapsulation can be improved, and loss of the program due to undesired joint breakdown can be prevented.

〔effect〕

As described above, according to the present invention, the PN junction of the memory cell is deeper than the PN junction of the transistor constituting the peripheral circuit, so that undesired junction breakdown can be prevented even if the integration density of the memory cell is increased.

[Brief explanation of drawings]

Figure 1 shows a cross section (2) of an embodiment of the present invention, Figure 2, and Figure 3.
Each figure is a sectional view showing a part of a conventional example. 1... Semiconductor substrate, 8... PN junction of transistor, 23... PN junction of memory cell. Cold 2 figure

Claims (1)

[Claims] an array of addressable memory cells each having a PN junction and storing information depending on whether or not the PN junction is broken; and an array of addressable memory cells each having a PN junction and associated with the function of the array of memory cells A read-only memory device in which a functional peripheral circuit is formed on a single semiconductor substrate, characterized in that the PN junction of the memory cell is formed at a deeper position than the PN junction of a transistor constituting the peripheral circuit. Dedicated storage device.